Abstract: Clock skew may be detected measured and compensated for using phase detectors and variable delay adjusters. Phase detectors may be distributed throughout a clock distribution network and may be configured to analyze two clock signals to determine how often one signal leads the other. The output of the phase detectors may be measured and counted over a large number of clock cycles. The difference between the number of times one signal leads or lags behind the other may be used to determine the amount of delay to apply to the leading clock signal in order to minimize (reduce) skew between the two clock signals. The same techniques for detecting and measuring clock skew may also be used to detect and measure jitter in the clock signals. By configuring variable delay adjusters on clock signals, the amount of jitter in the clock signals can be measured or characterized.

Abstract: A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.

Abstract: An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.

Abstract: An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit.

Abstract: Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is synchronized by one or more clocks. For example, an operation performed by circuitry on one side of the die may need to occur at precisely the same time as another operation performed by circuitry on the other side of the die. In order to assure synchronicity of these events, a clock grid may be provided in the IC that is driven by virtual leaf driver nodes. The clock tree driving the clock grid may include a tier of leaf buffers. The output of a leaf buffer may be split, and the branches of the output connected to separate points on the clock grid.