Patents by Inventor Ravindra A. Kapre
Ravindra A. Kapre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11810616Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.Type: GrantFiled: May 19, 2022Date of Patent: November 7, 2023Assignee: Infineon Technologies LLCInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
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Publication number: 20220359006Abstract: A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N×analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.Type: ApplicationFiled: May 19, 2022Publication date: November 10, 2022Applicant: Infineon Technologies LLCInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
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Patent number: 11355185Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.Type: GrantFiled: March 24, 2020Date of Patent: June 7, 2022Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
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Publication number: 20210159346Abstract: A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar, Vineet Agrawal, Long Hinh, Santanu Kumar Samanta, Ravindra Kapre
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Publication number: 20210158868Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: ApplicationFiled: March 24, 2020Publication date: May 27, 2021Applicant: Cypress Semiconductor CorporationInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Argrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
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Patent number: 11017851Abstract: A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N×analog values corresponding to the N×levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.Type: GrantFiled: March 24, 2020Date of Patent: May 25, 2021Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Venkataraman Prabhakar, Krishnaswamy Ramkumar, Vineet Agrawal, Long Hinh, Swatilekha Saha, Santanu Kumar Samanta, Michael Amundson, Ravindra Kapre
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Publication number: 20140098598Abstract: A current-limiting device may be configured to be placed along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.Type: ApplicationFiled: July 23, 2013Publication date: April 10, 2014Applicant: CYPRESS SEMICONDUCTOR CORPORATIONInventors: RavIndra Kapre, Shahin Sharifzadeh
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Patent number: 8143129Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.Type: GrantFiled: August 4, 2008Date of Patent: March 27, 2012Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Ravindra Kapre, Jeremy Warren
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Patent number: 8093128Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.Type: GrantFiled: May 22, 2008Date of Patent: January 10, 2012Assignee: Cypress Semiconductor CorporationInventors: William W. C. Koutny, Jr., Sam Geha, Igor Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sagy Levy, Ravindra Kapre, Jeremy Warren
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Patent number: 7629653Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.Type: GrantFiled: July 13, 2007Date of Patent: December 8, 2009Assignee: Cypress Semiconductor CorporationInventors: Sharmin Sadoughi, Krishnaswamy Ramkumar, Ravindra Kapre, Igor Polishchuk, Maroun Khoury
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Publication number: 20080296661Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.Type: ApplicationFiled: August 4, 2008Publication date: December 4, 2008Inventors: Krishnaswamy Ramkumar, Ravindra Kapre, Jeremy Warren
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Publication number: 20080293207Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.Type: ApplicationFiled: May 22, 2008Publication date: November 27, 2008Inventors: William W.C. Koutny, JR., Sam Geha, Igor Kouznetsov, Krishnaswamy Ramkumar, Fredrick B. Jenne, Sagy Levy, Ravindra Kapre, Jeremy Warren
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Publication number: 20070210339Abstract: In one embodiment, a shared contact structure electrically connects a gate, a diffusion region, and another diffusion region. The shared contact structure may comprise a trench that exposes the gate, the diffusion region, and the other diffusion region. The trench may be filled with a metal to form electrical connections. The trench may be formed in a dielectric layer using a self-aligned etch step, for example.Type: ApplicationFiled: March 9, 2006Publication date: September 13, 2007Inventors: Geethakrishnan Narasimhan, Bartosz Banachowicz, Ravindra Kapre
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Patent number: 7256087Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.Type: GrantFiled: December 21, 2004Date of Patent: August 14, 2007Assignee: Cypress Semiconductor CorporationInventors: Sharmin Sadoughi, Krishnaswamy Ramkumar, Ravindra Kapre, Igor Polishchuk, Maroun Khoury
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Publication number: 20050286295Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.Type: ApplicationFiled: June 25, 2004Publication date: December 29, 2005Inventors: Ravindra Kapre, Shahin Sharifzadeh
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Patent number: 6331468Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.Type: GrantFiled: May 11, 1998Date of Patent: December 18, 2001Assignee: LSI Logic CorporationInventors: Sheldon Aronowitz, Helmut Puchner, Ravindra A. Kapre, James P. Kimball