Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Abstract: Method and system for providing increased frequency of flash memories compatible to Serial Peripheral Interface (SPI) bus protocol by delayed data capturing so that system boot loader down load time reduces for a given memory configuration. Methods and systems are provided for operating the memory at the device rated frequency.

Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: A power management controller controls a power mode associated with a memory device and includes a logic element operative to provide a power mode control signal. The logic element is responsive to first and second control signals, the second control signal being a delayed version of the first control signal. The first control signal is provided by a processing device, and the power mode control signal transitions (i) inactive before a chip select signal transitions active and/or (ii) active after the chip select signal transitions inactive. The chip select signal controls the memory device, and the power mode control signal controls the power mode associated with the memory device. A corresponding method, computer-readable medium, and electronic system are also disclosed. A method that selects a power control mode associated with the power management controller, which controls a power mode associated with the memory device, is also disclosed.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

Abstract: An interrupt sensitive extract byte instruction scheme is presented herein. The interrupt sensitive extract by instruction extracts bytes from data, depending on the presence of an interrupt. The extract byte instruction extracts bytes from data in the absence of the interrupt and does not extract bytes in the presence of the interrupt. The interrupt can be triggered by a set of counters that count the number of extracted bytes. By loading the counters with a particular number, the interrupt can be generated when the particular number of data bytes is extracted.

Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

Abstract: Presented herein are system(s), method(s), and apparatus for an audio decoding accelerator. In one embodiment, there is presented an audio decoder for decoding audio data. The audio decoder comprises a controller and a computation engine. The controller receives the audio data, and provides parameters, where the parameters are associated with the audio data. The computation engine calculates at least one of a plurality of predetermined functions for said parameters.

Abstract: Presented herein is a unified decoder architecture. A system comprises a video decoder, instruction memory, and a host processor. The video decoder decodes the video data encoded with the particular standard. The instruction memory stores a first set of instructions and a second set of instructions. The first set of instructions are for decoding encoded video data according to a first encoding standard. The second set of instruction are for decoding encoded video data according to a second encoding standard. The host processor provides an indication to the video decoder indicating the particular encoding standard. The video decoder executes the first set of instructions if the indication indicates that the particular encoding standard is the first encoding standard and executes the second set of instructions if the indication indicates that the particular encoding standard is the second encoding standard.

Abstract: An interrupt sensitive extract byte instruction scheme is presented herein. The interrupt sensitive extract by instruction extracts bytes from data, depending on the presence of an interrupt. The extract byte instruction extracts bytes from data in the absence of the interrupt and does not extract bytes in the presence of the interrupt. The interrupt can be triggered by a set of counters that count the number of extracted bytes. By loading the counters with a particular number, the interrupt can be generated when the particular number of data bytes is extracted.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.