Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: In response to reloading an instruction from main memory for storing in an instruction cache in a superscalar data processing system, a particular instruction category in which the instruction belongs is selected from multiple instruction categories. Types of data processing system resources required for instruction execution and a quantity of each type of resource required are determined. Thereafter, a plurality of decode bits are calculated, wherein the decode bits represent a particular instruction category in which the instruction belongs and the type and quantity of each data processing system resource required for execution of the instruction. Thereafter, the instruction and the predecode bits are stored in instruction cache.

Abstract: A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss occurs. When a prefetch miss occurs, the BAB is checked to see if instructions corresponding to the target address are available. If they are available, these instructions are copied into an appropriate buffer. If the instructions corresponding to the target address are unavailable, these instructions are fetched from the I-cache and placed into a buffer and, selectively, into the BAB. The BAB only maintains branch target addresses that have not been previously scanned and that cannot be prefetched in time. This allows for smaller buffer sizes, and resulting quicker access time, when checking the BAB for instructions to be executed by a processor.