Patents by Inventor Ravindra P. Saraf

Ravindra P. Saraf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sub-numa clustering
    Patent number: 8862828
    Abstract: Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Intel Corporation
    Inventors: Ravindra P. Saraf, Rahul Pal, Ashok Jagannathan
  • SUB-NUMA CLUSTERING
    Publication number: 20140006715
    Abstract: Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
    Type: Application
    Filed: August 13, 2012
    Publication date: January 2, 2014
    Applicant: INTEL CORPORATION
    Inventors: Ravindra P. Saraf, Rahul Pal, Ashok Jagannathan
  • Providing a directory cache for peripheral devices
    Patent number: 8489822
    Abstract: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: July 16, 2013
    Assignee: Intel Corporation
    Inventors: Andrew Y. Sun, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Ravindra P. Saraf
  • Providing A Directory Cache For Peripheral Devices
    Publication number: 20120131282
    Abstract: In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
    Type: Application
    Filed: November 23, 2010
    Publication date: May 24, 2012
    Inventors: Andrew Y. Sun, Henk G. Neefs, Rahul Pal, Manoj K. Arora, Ravindra P. Saraf