Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.

Abstract: When interfacing with a host, a networking device can handle a first data like Bulk Data Receive. The networking device can receive the first data and read a first queue entry from a receive queue in the host memory. In response to the read first queue entry, the networking device can write the first data to an unpinned memory in the host memory. The networking device can also handle a second data with a Receive Packet in Ring (RPIR) queue. The networking device can receive the second data and write the second data to a pinned memory in the host memory. The RPIR queue can be separate from or overlaid on the receive queue. High throughput and low-latency operation can be achieved. The use of a RPIR queue can facilitate the efficiency of resource utilization in the reception of data messages.

Abstract: A storage processor is constructed on or within an interconnected circuit (IC) chip. The storage processor has a plurality of ports operable to send and/or receive messages to/from storage devices. An output indication circuit is associated with each output port. The indication circuit indicates that data is ready to be transmitted to a storage device from the particular output port. A crossover circuit is interposed between the ports. The crossover circuit has a memory that can store data. When data is received at a port, the storage processor can store the incoming data to the crossover circuit. A memory is also present on the chip. The memory holds data that relates incoming data to outgoing data. Thus, when data comes into the storage processor, the storage processor can determine a specific course of action for that data based upon the information stored in this memory. The chip also has a plurality of processing sub-units coupled to the crossover switch.