Patents by Inventor Ravindra Soman

Ravindra Soman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7517768
    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: April 14, 2009
    Assignee: Intel Corporation
    Inventors: Ravindra Soman, Anand Murthy, Peter VanDerVoorn, Shahriar Ahmed
  • Patent number: 7473591
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Publication number: 20060113634
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Application
    Filed: November 7, 2005
    Publication date: June 1, 2006
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Publication number: 20060084216
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: December 1, 2005
    Publication date: April 20, 2006
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Patent number: 7019326
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Patent number: 7005359
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Patent number: 6933589
    Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Boyan Boyanov, Ravindra Soman, Robert S. Chau
  • Patent number: 6927140
    Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: August 9, 2005
    Assignee: Intel Corporation
    Inventors: Ravindra Soman, Anand Murthy
  • Publication number: 20050106792
    Abstract: Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.
    Type: Application
    Filed: November 14, 2003
    Publication date: May 19, 2005
    Inventors: Stephen Cea, Ravindra Soman, Ramune Nagisetty, Sunit Tyagi, Sanjay Natarajan
  • Publication number: 20050104160
    Abstract: A bipolar transistor and its fabrication are described. The extrinsic base region is formed by growing a second, more heavily doped, epitaxial layer over a first epitaxial layer. The second layer extends under, and is insulated from, an overlying polysilicon emitter pedestal.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 19, 2005
    Inventors: Shahriar Ahmed, Ravindra Soman, Anand Murthy, Mark Bohr
  • Publication number: 20050079660
    Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.
    Type: Application
    Filed: August 11, 2004
    Publication date: April 14, 2005
    Inventors: Anand Murthy, Boyan Boyanov, Ravindra Soman, Robert Chau
  • Patent number: 6812086
    Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 2, 2004
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Boyan Boyanov, Ravindra Soman, Robert S. Chau
  • Publication number: 20040192002
    Abstract: A bipolar transistor with a SiGe:C film and a seed layer forming beneath the SiGe:C film and methods of making same. The method includes placing a substrate in a reactor chamber and introducing a silicon source gas into the reactor chamber to form a silicon seed layer. The reactor chamber is maintained at a pressure below 45 Torr and a temperature between about 700° C. and 850° C. After the seed layer is formed, the silicon source gas is stopped. The reactor chamber is then simultaneously adjusted to a pressure between about 70 Torr and 90 Torr and a temperature between about 600° C. and 650° C. The silicon source gas, a germanium source gas, and a carbon source gas are introduced to form the SiGe:C film on the seed layer.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Ravindra Soman, Anand Murthy, Peter VanDerVoorn, Shahriar Ahmed
  • Patent number: 6723622
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov
  • Publication number: 20040048439
    Abstract: A method for forming a base of a bipolar transistor. A narrow base is formed using a flash of boron doping gas in a reaction chamber to create a narrow base with high boron concentration. This method allows for reliable formation of a base with high boron concentration while maintaining manageability in controlling deposition of other materials in a substrate.
    Type: Application
    Filed: August 21, 2002
    Publication date: March 11, 2004
    Inventors: Ravindra Soman, Anand Murthy
  • Publication number: 20040014276
    Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.
    Type: Application
    Filed: July 16, 2002
    Publication date: January 22, 2004
    Inventors: Anand S. Murthy, Boyan Boyanov, Ravindra Soman, Robert S. Chau
  • Publication number: 20030207127
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Application
    Filed: May 30, 2003
    Publication date: November 6, 2003
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov
  • Publication number: 20030157787
    Abstract: A composite of germanium film for a semiconductor device and methods of making the same. The method comprises growing a graded germanium film on a semiconductor substrate in a deposition chamber while simultaneously decreasing a deposition temperature and decreasing a silicon source gas and increasing a germanium source gas over a predetermined amount of time. The graded germanium film comprises an ultra-thin silicon-germanium buffer layer and a germanium film.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 21, 2003
    Inventors: Anand Murthy, Ravindra Soman, Boyan Boyanov