Patents by Inventor Ravindra Tanikella
Ravindra Tanikella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230088392Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a first via is through the core, where the first via directly contacts the core. In an embodiment, a second via is through the core, and a sleeve is around the second via. In an embodiment, the sleeve comprises a material with a thermal conductivity that is greater than a thermal conductivity of the second via.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Srinivas V. PIETAMBARAM, Gang DUAN, Rahul N. MANEPALLI, Ravindra TANIKELLA, Sameer PAITAL
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Publication number: 20230087838Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a protective coating for an edge of a glass layer, in particular a glass core within a substrate of a package, where the protective coating serves to protect the edge of the glass core and fill in cracks at the edges of the glass. This protective coating will decrease cracking during stresses applied to the glass layer during manufacturing or operation. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Rahul N. MANEPALLI, Srinivas V. PIETAMBARAM, Ravindra TANIKELLA, Sameer PAITAL, Gang DUAN
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Publication number: 20230092740Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a hole is through a thickness of the core, and a plug fills the hole, where the plug comprises a polymeric material. In an embodiment, first layers are over the core, where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI, Ravindra TANIKELLA
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Patent number: 8530890Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: GrantFiled: June 26, 2012Date of Patent: September 10, 2013Assignee: Intel CorporationInventors: Nachiket Raravikar, Ravindra Tanikella
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Publication number: 20120270008Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: ApplicationFiled: June 26, 2012Publication date: October 25, 2012Applicant: Intel CorporationInventors: Nachiket Raravikar, Ravindra Tanikella
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Patent number: 8222750Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: GrantFiled: February 2, 2009Date of Patent: July 17, 2012Assignee: Intel CorporationInventors: Nachiket Raravikar, Ravindra Tanikella
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Patent number: 7790598Abstract: According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located in an opening formed through both the solder resist material and the mask material, and removing the mask material after the reflowing of the solder.Type: GrantFiled: February 27, 2009Date of Patent: September 7, 2010Assignee: Intel CorporationInventors: Mengzhi Pang, Christopher J. Bahr, Ravindra Tanikella, Charan Gurumurthy
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Publication number: 20090196000Abstract: According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located in an opening formed through both the solder resist material and the mask material, and removing the mask material after the reflowing of the solder.Type: ApplicationFiled: February 27, 2009Publication date: August 6, 2009Inventors: Mengzhi Pang, Christopher J. Bahr, Ravindra Tanikella, Charan Gurumurthy
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Publication number: 20090192241Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: ApplicationFiled: February 2, 2009Publication date: July 30, 2009Inventors: Nachiket Raravikar, Ravindra Tanikella
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Patent number: 7534648Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: GrantFiled: June 29, 2006Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Nachiket Raravikar, Ravindra Tanikella
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Patent number: 7517788Abstract: According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located in an opening formed through both the solder resist material and the mask material, and removing the mask material after the reflowing of the solder.Type: GrantFiled: December 29, 2005Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Mengzhi Pang, Christopher J. Bahr, Ravindra Tanikella, Charan Gurumurthy
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Publication number: 20080087986Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: ApplicationFiled: November 27, 2007Publication date: April 17, 2008Inventor: Ravindra Tanikella
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Publication number: 20080012155Abstract: A composite material including an arrangement of approximately aligned nanofilaments overlying at least another arrangement of approximately aligned nanofilaments, the longitudinal axis of the nanotubes of the first arrangement being approximately perpendicular to the longitudinal axis of the nanotubes of the other arrangement, and the arrangements forming at least one array. A resin material having nanoparticles dispersed throughout is disposed among the array(s) of nanofilaments, and cured, and openings may be formed into or through the composite material corresponding to spaces provided in the array of nanofilaments. A composite material according to embodiments forms a microelectronic substrate or some portion thereof, such as a substrate core.Type: ApplicationFiled: June 29, 2006Publication date: January 17, 2008Inventors: Nachiket Raravikar, Ravindra Tanikella
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Publication number: 20070152024Abstract: According to some embodiments, a method, apparatus, and system are provided. In some embodiments, the method includes providing solder resist material on a surface of a substrate, applying mask material on top of the solder resist material, reflowing solder located in an opening formed through both the solder resist material and the mask material, and removing the mask material after the reflowing of the solder.Type: ApplicationFiled: December 29, 2005Publication date: July 5, 2007Inventors: Mengzhi Pang, Christopher Bahr, Ravindra Tanikella, Charan Gurumuthy
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Publication number: 20070096083Abstract: Embodiments of substrate core polymer nanocomposite with nanoparticles and randomly oriented nanotubes and method for making the substrate core are generally described herein. Other embodiments may be described and claimed. In some embodiments, a nanotube suspension is combined with nanoparticle-impregnated polymer.Type: ApplicationFiled: October 27, 2005Publication date: May 3, 2007Inventors: Nachiket Raravikar, Ravindra Tanikella, Nirupama Chakrapani
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Publication number: 20060073624Abstract: A die-attach composition includes a resin such as a thermosetting resin, a hardener, and a low molecular weight oligomer diluent. A die-attach composition includes a polyimide in a major amount and a resin such as a thermosetting resin in a minor amount. The die-attach composition also includes a reactive polymer diluent. Combinations of the low molecular weight oligomer diluent and the reactive polymer diluent are included. The die-attach composition is applied to surface mount technology such as wire-bond dice. A computing system is also included that uses the die-attach composition.Type: ApplicationFiled: September 30, 2004Publication date: April 6, 2006Inventors: Rahul Manepalli, Ravindra Tanikella
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Publication number: 20060060956Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: ApplicationFiled: September 22, 2004Publication date: March 23, 2006Inventor: Ravindra Tanikella