Patents by Inventor Ravindra V. Tanikella
Ravindra V. Tanikella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11291122Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 22, 2017Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
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Publication number: 20200245472Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2017Publication date: July 30, 2020Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
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Patent number: 10211143Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: GrantFiled: November 1, 2016Date of Patent: February 19, 2019Assignee: Intel CorporationInventor: Ravindra V. Tanikella
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Publication number: 20170148723Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: ApplicationFiled: November 1, 2016Publication date: May 25, 2017Inventor: Ravindra V. Tanikella
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Patent number: 9484277Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: GrantFiled: June 27, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventor: Ravindra V. Tanikella
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Patent number: 9147603Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.Type: GrantFiled: January 23, 2014Date of Patent: September 29, 2015Assignee: Intel CorporationInventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella
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Publication number: 20150206793Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Inventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella
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Publication number: 20140312101Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: ApplicationFiled: June 27, 2014Publication date: October 23, 2014Inventor: RAVINDRA V. TANIKELLA
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Patent number: 8796825Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: GrantFiled: January 18, 2012Date of Patent: August 5, 2014Assignee: Intel CorporationInventor: Ravindra V. Tanikella
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Publication number: 20120181687Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Inventor: RAVINDRA V. TANIKELLA
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Patent number: 8129823Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: GrantFiled: November 27, 2007Date of Patent: March 6, 2012Assignee: Intel CorporationInventor: Ravindra V. Tanikella
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Patent number: 7816487Abstract: A die-attach composition includes a resin such as a thermosetting resin, a hardener, and a low molecular weight oligomer diluent. A die-attach composition includes a polyimide in a major amount and a resin such as a thermosetting resin in a minor amount. The die-attach composition also includes a reactive polymer diluent. Combinations of the low molecular weight oligomer diluent and the reactive polymer diluent are included. The die-attach composition is applied to surface mount technology such as wire-bond dice. A computing system is also included that uses the die-attach composition.Type: GrantFiled: September 30, 2004Date of Patent: October 19, 2010Assignee: Intel CorporationInventors: Rahul N. Manepalli, Ravindra V. Tanikella
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Patent number: 7335608Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).Type: GrantFiled: September 22, 2004Date of Patent: February 26, 2008Assignee: Intel CorporationInventor: Ravindra V. Tanikella