Patents by Inventor Ravindra V. Tanikella

Ravindra V. Tanikella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11291122
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
  • Publication number: 20200245472
    Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 22, 2017
    Publication date: July 30, 2020
    Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
  • Patent number: 10211143
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Publication number: 20170148723
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Application
    Filed: November 1, 2016
    Publication date: May 25, 2017
    Inventor: Ravindra V. Tanikella
  • Patent number: 9484277
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Patent number: 9147603
    Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 29, 2015
    Assignee: Intel Corporation
    Inventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella
  • Publication number: 20150206793
    Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella
  • Publication number: 20140312101
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Application
    Filed: June 27, 2014
    Publication date: October 23, 2014
    Inventor: RAVINDRA V. TANIKELLA
  • Patent number: 8796825
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Publication number: 20120181687
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Application
    Filed: January 18, 2012
    Publication date: July 19, 2012
    Inventor: RAVINDRA V. TANIKELLA
  • Patent number: 8129823
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Patent number: 7816487
    Abstract: A die-attach composition includes a resin such as a thermosetting resin, a hardener, and a low molecular weight oligomer diluent. A die-attach composition includes a polyimide in a major amount and a resin such as a thermosetting resin in a minor amount. The die-attach composition also includes a reactive polymer diluent. Combinations of the low molecular weight oligomer diluent and the reactive polymer diluent are included. The die-attach composition is applied to surface mount technology such as wire-bond dice. A computing system is also included that uses the die-attach composition.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Rahul N. Manepalli, Ravindra V. Tanikella
  • Patent number: 7335608
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella