Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.

Abstract: In some embodiments, a method for optimizing EFIFO latency may include one or more of the following steps: (a) counting each clock cycle from a read clock for a predetermined period of time, (b) counting each clock cycle from a write clock for a predetermined period of time, (c) comparing the counted read clock cycles to the write clock cycles to obtain a difference between the counted clock cycles, (d) adjusting a watermark for a queue based upon the difference between the counted clock cycles, (e) receiving a timeout signal, (f) terminating counting of the clock cycles of the read clock and write clock, and (g) initiating another optimization process after termination.

Abstract: A method for verifying a protocol employed by a protocol handler. In an embodiment, the method includes verifying a Receive Link Layer defined within a protocol handler with Open Vera Assertions. The Receive Link Layer may include a plurality of interfaces and is configured for separating data into a series of packets. Further, a plurality of features included within the series of packets are monitored with Open Vera Assertions. Additionally, functional coverage is measured with coverage statements based upon Open Vera Assertions. Finally, Open Vera Assertion severity and error isolation is controlled through message logging.

Abstract: A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one clock cycle. The CRC polynomial is preferably incorporated into the hardware for each CRC calculation.