Patents by Inventor Ravindran Mohanavelu
Ravindran Mohanavelu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10069658Abstract: Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.Type: GrantFiled: September 23, 2015Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Salman Latif, Ravindran Mohanavelu, Sitaraman V. Iyer
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Patent number: 9825756Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: GrantFiled: December 9, 2016Date of Patent: November 21, 2017Assignee: INPHI CORPORATIONInventors: Halil Cirit, Karthik Gopalakrishnan, Pulkit Khandelwal, Ravindran Mohanavelu
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Publication number: 20170207908Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: ApplicationFiled: December 9, 2016Publication date: July 20, 2017Inventors: Halil CIRIT, Karthik GOPALAKRISHNAN, Pulkit KHANDELWAL, Ravindran MOHANAVELU
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Publication number: 20170085399Abstract: Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: Salman Latif, Ravindran Mohanavelu, Sitaraman V. Iyer
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Patent number: 9548858Abstract: The present invention is directed to communication systems. According to embodiments of the present invention, a communication system includes at least two communication lanes and a skew management module. The skew management module generates a control current based on output test patterns of the two communication lanes. The control current is integrated and compared to a reference voltage by a comparator, which generates an analog offset signal. A PLL of one of the communication lanes generates a corrected clock signal that is adjusted using the analog offset signal to remove or adjust the skew between the communication lanes. The corrected clock signal is used for output data. There are other embodiments as well.Type: GrantFiled: January 18, 2016Date of Patent: January 17, 2017Assignee: INPHI CORPORATIONInventors: Halil Cirit, Karthik Gopalakrishnan, Pulkit Khandelwal, Ravindran Mohanavelu
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Patent number: 9049001Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.Type: GrantFiled: April 30, 2013Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Yueming Jiang, Ravindran Mohanavelu, Michael W. Altmann
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Publication number: 20130243138Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.Type: ApplicationFiled: April 30, 2013Publication date: September 19, 2013Inventors: Yueming Jiang, Ravindran Mohanavelu, Michael W. Altmann
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Patent number: 8451969Abstract: Described herein are an apparatus, system and method for timing recovery in processors by means of a simplified receiver architecture that consumes less power consumption, has lower bit error rate (BER), and higher jitter tolerance. The apparatus comprises a phase interpolator to generate a clock signal; a first integrator to integrate a first portion of a data signal over a duration of a phase of the clock signal; a first sampler to sample the first integrated portion by means of the clock signal; a first circuit to store a first edge sample of the data signal; a second sampler to sample the stored first edge sample by means of the clock signal; and a clock data recovery unit to update the phase interpolator based at least on the sampled first integrated portion and sampled stored first edge sample of the data signal.Type: GrantFiled: March 15, 2011Date of Patent: May 28, 2013Assignee: Intel CorporationInventors: Yueming Jiang, Ravindran Mohanavelu, Michael W. Altmann
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Patent number: 7555670Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.Type: GrantFiled: October 26, 2005Date of Patent: June 30, 2009Assignee: Intel CorporationInventors: Ravindran Mohanavelu, Aaron K. Martin, Dawson Kesling, Joe Salmon, Mamun Ur Rashid
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Patent number: 7474127Abstract: According to one embodiment of the invention, a method for receiving a first signal in a first plurality of switching elements from a second plurality of switching elements, receiving a second signal in second plurality of switching elements from first plurality of switching elements, alternatively converting a first logic signal by first plurality of switching elements based on received first signal, and a second logic signal by the second plurality of switching elements based on received second signal. According to another embodiment of the invention, a system comprising a first plurality of switching elements to convert a first logic signal based on a predetermined input from a second plurality of switching elements, second plurality of switching elements to convert a second logic signal based on a predetermined input received from first plurality of switching elements; first and second plurality of switching elements to alternatively convert first and second logic signals.Type: GrantFiled: January 6, 2006Date of Patent: January 6, 2009Assignee: Intel CorporationInventor: Ravindran Mohanavelu
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Patent number: 7412221Abstract: A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk.Type: GrantFiled: March 29, 2005Date of Patent: August 12, 2008Assignee: Intel CorporationInventors: Ravindran Mohanavelu, Aaron K. Martin, William Dawson Kesling
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Patent number: 7315186Abstract: An equalized driver includes a voltage mode driver to drive data on a conductor and a current mode driver to provide equalization.Type: GrantFiled: June 6, 2005Date of Patent: January 1, 2008Assignee: Intel CorporationInventors: Aaron K. Martin, William Dawson Kesling, Ravindran Mohanavelu
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Publication number: 20070171117Abstract: According to one embodiment of the invention, a method for receiving a first signal in a first plurality of switching elements from a second plurality of switching elements, receiving a second signal in second plurality of switching elements from first plurality of switching elements, alternatively converting a first logic signal by first plurality of switching elements based on received first signal, and a second logic signal by the second plurality of switching elements based on received second signal. According to another embodiment of the invention, a system comprising a first plurality of switching elements to convert a first logic signal based on a predetermined input from a second plurality of switching elements, second plurality of switching elements to convert a second logic signal based on a predetermined input received from first plurality of switching elements; first and second plurality of switching elements to alternatively convert first and second logic signals.Type: ApplicationFiled: January 6, 2006Publication date: July 26, 2007Inventor: Ravindran Mohanavelu
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Patent number: 7212033Abstract: A level shifting device having an input side operating at a first voltage level, an output side operating at a second voltage level and a level shifting circuit which connects the input and output sides. The input circuit receives an input signal referenced to the first voltage level and provides separate outputs corresponding to transitions of the input signal. The level shifting circuit includes MOSFETS having the gates connected respectively to each output of the input circuit; and the source-drain path coupled between the second voltage and a reference for the first voltage. The output side has a differential topology, and includes a first circuit which samples signals corresponding to the transitions of the input signal, holds the sample between transitions, and an output circuit which receives the held sample signal in differential form and converts it to single-ended form for use by other circuits. The circuit also blocks input signals when common mode transients are present.Type: GrantFiled: March 25, 2005Date of Patent: May 1, 2007Assignee: International Rectifier CorporationInventors: Muthu Subramanian, Ravindran Mohanavelu
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Publication number: 20070091712Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional clock port capable of being statically configured to receive or to transmit a reference clock. In one embodiment, the chip includes a first port to receive data and a second port, wherein the chip repeats at least a portion of the data that it receives on the first port to a transmitter at the second port. Other embodiments are described and claimed.Type: ApplicationFiled: October 26, 2005Publication date: April 26, 2007Inventors: Ravindran Mohanavelu, Aaron Martin, Dawson Kesling, Joe Salmon, Mamun Rashid
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Publication number: 20060290439Abstract: An equalized driver includes a voltage mode driver to drive data on a conductor and a current mode driver to provide equalization.Type: ApplicationFiled: June 6, 2005Publication date: December 28, 2006Inventors: Aaron Martin, William Kesling, Ravindran Mohanavelu
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Publication number: 20060223480Abstract: A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk.Type: ApplicationFiled: March 29, 2005Publication date: October 5, 2006Inventors: Ravindran Mohanavelu, Aaron Martin, William Kesling
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Publication number: 20060198235Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.Type: ApplicationFiled: May 11, 2006Publication date: September 7, 2006Inventors: Ravindran Mohanavelu, Payam Heydari
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Publication number: 20050229120Abstract: A level shifting device having an input side operating at a first voltage level, an output side operating at a second voltage level and a level shifting circuit which connects the input and output sides. The input circuit receives an input signal referenced to the first voltage level and provides separate outputs corresponding to transitions of the input signal. The level shifting circuit includes MOSFETS having the gates connected respectively to each output of the input circuit; and the source-drain path coupled between the second voltage and a reference for the first voltage. The output side has a differential topology, and includes a first circuit which samples signals corresponding to the transitions of the input signal, holds the sample between transitions, and an output circuit which receives the held sample signal in differential form and converts it to single-ended form for use by other circuits. The circuit also blocks input signals when common mode transients are present.Type: ApplicationFiled: March 25, 2005Publication date: October 13, 2005Inventors: Muthu Subramanian, Ravindran Mohanavelu
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Publication number: 20050030076Abstract: A clock and data recovery system using a distributed variable delay line is provided. The clock and data recovery system can use a delay-locked loop methodology to align a local clock with an incoming data stream. The variable delay line can include a transmission line coupled with a plurality of variable capacitors responsive to a control voltage. The variable delay line can also have a ladder configuration of multiple LC subcircuits each having a variable impedance responsive to a control voltage.Type: ApplicationFiled: May 28, 2004Publication date: February 10, 2005Inventors: Ravindran Mohanavelu, Payam Heydari