Abstract: A method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images are provided. The method of rendering high resolution images based on sub-band encoded data of an image includes steps of performing downscaling of a selected image, creating a time-stamped downscaled image, extracting sub-band information associated with the selected image at one instance in time, compressing the downscaled image and the sub-band information, and decompressing and adding the sub-band information with extrapolated downscaled image to reconstruct and render high resolution image.

Abstract: A method and apparatus for storing, processing and reconstructing full resolution image out of sub band encoded images are provided. The method of rendering high resolution images based on sub-band encoded data of an image includes steps of performing downscaling of a selected image, creating a time-stamped downscaled image, extracting sub-band information associated with the selected image at one instance in time, compressing the downscaled image and the sub-band information, and decompressing and adding the sub-band information with extrapolated downscaled image to reconstruct and render high resolution image.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.

Abstract: A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.