Patents by Inventor Ravindranath Shrivastava
Ravindranath Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11405035Abstract: A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.Type: GrantFiled: July 13, 2021Date of Patent: August 2, 2022Assignee: PSEMI CORPORATIONInventors: Alper Genc, Fleming Lam, Eric S. Shapiro, Ravindranath Shrivastava
-
Publication number: 20210021257Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.Type: ApplicationFiled: July 30, 2020Publication date: January 21, 2021Inventors: Ravindranath Shrivastava, Peter Bacon
-
Patent number: 10312885Abstract: A self-matching phase shifter/attenuator including several incremental impedance matched phase shifter/attenuator elements is disclosed. Each incremental impedance matched phase shifter element comprises a reactive component (such as either a capacitor or inductor) that can be coupled in shunt to the signal path. The shunt reactive component is coupled in series with a ground switch. When closed, the ground switch connects the shunt reactive component to ground. When the ground switch is open, the switch removes the shunt reactive component from the circuit. In addition, each incremental impedance matched phase shifter element comprises a series reactive component having a reactance that is typically equal and inverse of that of the shunt reactive component.Type: GrantFiled: February 15, 2017Date of Patent: June 4, 2019Assignee: pSemi CorporationInventor: Ravindranath Shrivastava
-
Patent number: 10205439Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.Type: GrantFiled: September 2, 2016Date of Patent: February 12, 2019Assignee: pSemi CorporationInventors: Ravindranath Shrivastava, Kristian Madsen
-
Patent number: 10193531Abstract: Digital step attenuator (DSA) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (IC) die (or “chip”), and provide flexibility of design for various applications. Embodiments utilize one or more architectural features and/or design techniques to achieve such characteristics, including reduced resistor and FET switch sizes, reduced series stack sizes, unidirectional input power configurations, capacitor compensation to match bandwidth characteristics, activating low-power thermometer-weighted attenuator cells only after activating higher power thermometer-weighted attenuator cells, and reducing signal transients (glitches) using a thermometer-weighted configuration of attenuator cells.Type: GrantFiled: January 14, 2016Date of Patent: January 29, 2019Assignee: pSemi CorporationInventor: Ravindranath Shrivastava
-
Publication number: 20180234080Abstract: A self-matching phase shifter/attenuator including several incremental impedance matched phase shifter/attenuator elements is disclosed. Each incremental impedance matched phase shifter element comprises a reactive component (such as either a capacitor or inductor) that can be coupled in shunt to the signal path. The shunt reactive component is coupled in series with a ground switch. When closed, the ground switch connects the shunt reactive component to ground. When the ground switch is open, the switch removes the shunt reactive component from the circuit. In addition, each incremental impedance matched phase shifter element comprises a series reactive component having a reactance that is typically equal and inverse of that of the shunt reactive component.Type: ApplicationFiled: February 15, 2017Publication date: August 16, 2018Inventor: Ravindranath Shrivastava
-
Publication number: 20180212590Abstract: A phase shifter cell and multiple coupled phase shifter cells that mitigate signal glitches arising from phase state changes by a combination of design architecture and control signal timing. Specifically, one or more of the following three concepts are employed to mitigate insertion loss glitches and control phase behavior during phase state transitions: the timing of switching for each switched half-cell (e.g., including series and/or shunt reactance elements, such as inductors and/or capacitors) within a phase shifter cell is controlled in such a way that the reactance elements do not all switch at the same time; use of a “make before break” timing scheme for combination or “multi-state” phase shifter cells; and/or arranging the timing of each phase shifter cell in a set of multiple coupled phase shifter cells such that the individual cells do not all switch at the same time.Type: ApplicationFiled: January 24, 2017Publication date: July 26, 2018Inventors: Ravindranath Shrivastava, Peter Bacon
-
Patent number: 9935614Abstract: Multi-state radio frequency (RF) attenuator configurations that include bridged-T type, pi-type, and T-type structures each having a programmable throughput section and a coupled programmable shunt section. The throughput sections and shunt sections may be configured in various combinations of parallel and serial fixed or selectable resistance elements such that multiple resistance states and impedance matching states can be programmatically selected, and may include stacked switch elements to withstand applied voltages to a specified design level.Type: GrantFiled: October 31, 2016Date of Patent: April 3, 2018Assignee: pSemi CorporationInventor: Ravindranath Shrivastava
-
Patent number: 9917613Abstract: A digitally controlled phase shifter and (optional) attenuator circuit that has both a broad range as well as a fine-tuning resolution. Embodiments maintain a full 360° phase range while providing nth-bit least-significant bit (LSB) resolution across the entire range of possible phase shift and attenuation states, and compensate for the effect of frequency and/or PVT variations. In embodiments, two or more range partitionings can be defined that can be monotonic over respective sub-ranges while providing full coverage when combined. One such partitioning is a “coarse+fine” architecture. Embodiments of the coarse+fine architecture provide for greater than 360° of range for phase shifting and more than the total nominal design level for attenuation, and provide for fine ranges for both phase shifting and attenuation that are greater than the LSB of the corresponding coarse ranges for phase shifting and attenuation.Type: GrantFiled: January 24, 2017Date of Patent: March 13, 2018Assignee: pSemi CorporationInventors: Peter Bacon, Matt Allison, Ravindranath Shrivastava
-
Publication number: 20170207769Abstract: Digital step attenuator (DSA) configurations which are capable of handling high power signals, have low insertion loss and parasitic effects, have few or no glitches between state transitions, have minimal effect on chip area and power dissipation on an integrated circuit (IC) die (or “chip”), and provide flexibility of design for various applications. Embodiments utilize one or more architectural features and/or design techniques to achieve such characteristics, including reduced resistor and FET switch sizes, reduced series stack sizes, unidirectional input power configurations, capacitor compensation to match bandwidth characteristics, activating low-power thermometer-weighted attenuator cells only after activating higher power thermometer-weighted attenuator cells, and reducing signal transients (glitches) using a thermometer-weighted configuration of attenuator cells.Type: ApplicationFiled: January 14, 2016Publication date: July 20, 2017Inventor: Ravindranath Shrivastava
-
Publication number: 20170104471Abstract: Multi-state radio frequency (RF) attenuator configurations that include bridged-T type, pi-type, and T-type structures each having a programmable throughput section and a coupled programmable shunt section. The throughput sections and shunt sections may be configured in various combinations of parallel and serial fixed or selectable resistance elements such that multiple resistance states and impedance matching states can be programmatically selected, and may include stacked switch elements to withstand applied voltages to a specified design level.Type: ApplicationFiled: October 31, 2016Publication date: April 13, 2017Inventor: Ravindranath Shrivastava
-
Patent number: 9531359Abstract: Multi-state radio frequency (RF) attenuator configurations that include bridged-T type, pi-type, and T-type structures each having a programmable throughput section and a coupled programmable shunt section. The throughput sections and shunt sections may be configured in various combinations of parallel and serial fixed or selectable resistance elements such that multiple resistance states and impedance matching states can be programmatically selected, and may include stacked switch elements to withstand applied voltages to a specified design level.Type: GrantFiled: October 8, 2015Date of Patent: December 27, 2016Assignee: Peregrine Semiconductor CorporationInventor: Ravindranath Shrivastava
-
Publication number: 20160373086Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Ravindranath Shrivastava, Kristian Madsen
-
Patent number: 9444432Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.Type: GrantFiled: November 11, 2014Date of Patent: September 13, 2016Assignee: Peregrine Semiconductor CorporationInventors: Ravindranath Shrivastava, Kristian Madsen
-
Publication number: 20160134259Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Inventors: Ravindranath Shrivastava, Kristian Madsen