Abstract: Technologies for split key security include a payment device to generate a key encryption key and a first key encryption key part. The payment device generates a second key encryption key part based on the key encryption key and the first key encryption key part and deletes the key encryption key in response to generating the second key encryption key part. Further, the payment device stores the first key encryption key part to a secure memory of a security co-processor of the payment device and the second key encryption key part to a secure memory of a secondary processor of the payment device. The secondary processor is electrically coupled to a backup energy source.

Abstract: Technologies for split key security include a payment device to generate a key encryption key and a first key encryption key part. The payment device generates a second key encryption key part based on the key encryption key and the first key encryption key part and deletes the key encryption key in response to generating the second key encryption key part. Further, the payment device stores the first key encryption key part to a secure memory of a security co-processor of the payment device and the second key encryption key part to a secure memory of a secondary processor of the payment device. The secondary processor is electrically coupled to a backup energy source.

Abstract: Systems, methods, and devices are directed to an electronic device that includes a first wireless communication module configured to facilitate transmission and reception of data via a wireless communication link and a first secure element while a wireless communication device includes a processor, an operating system executed by the processor, a second wireless communication module configured to facilitate transmission and reception of data via the wireless communication link, and a second secure element. The second secure element exchanges information with the first secure element via the wireless communication link to establish a secure channel within the wireless communication link, and the wireless communication device employs logic configured to route the data to the second secure element for processing prior to forwarding the data to the operating system, upon establishing the secure channel.

Abstract: Systems, methods, and devices are directed to an electronic device that includes a first wireless communication module configured to facilitate transmission and reception of data via a wireless communication link and a first secure element while a wireless communication device includes a processor, an operating system executed by the processor, a second wireless communication module configured to facilitate transmission and reception of data via the wireless communication link, and a second secure element. The second secure element exchanges information with the first secure element via the wireless communication link to establish a secure channel within the wireless communication link, and the wireless communication device employs logic configured to route the data to the second secure element for processing prior to forwarding the data to the operating system, upon establishing the secure channel.

Abstract: In one embodiment a controller comprises logic to receive a payment request for a purchase transaction, wherein the payment request comprises transaction information associated with the purchase transaction, present at least a portion of the transaction information on a user interface, receive payment source data from a remote resource, securely wrap the payment source data and transmit the payment source data to a remote device. Other embodiments may be described.

Abstract: In one embodiment a controller comprises logic to receive a request for a credential to authenticate a user for a transaction, in response to a determination that a credential which satisfies the request resides on a memory module, execute an authentication routine to authenticate a user of the controller, in response to a successful authentication, retrieve the credential from the memory module, and provide a token to certify the credential in response to the request. Other embodiments may be described.

Abstract: Methods and apparatus relating to low power optimized voltage regulators are described. In one embodiment, a voltage regulator controller may cause leakage current from a load to drain a capacitor (e.g., coupled in parallel with the load) during a reduced power state.

Abstract: In some embodiments an integrated circuit package includes a coaxial arrangement of one or more ground via surrounding a signal via. The one or more ground via and the signal via extend through the package to allow transmission of signals between an integrated circuit and a board. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to low power optimized voltage regulators are described. In one embodiment, a voltage regulator controller may cause leakage current from a load to drain a capacitor (e.g., coupled in parallel with the load) during a reduced power state. Other embodiments are also disclosed.

Abstract: Various embodiments of a power device configuration along with adaptive control mechanisms are described. In one embodiment, for example, an apparatus may comprise multiple power switching devices. One or more of the power switching devices may be selected and/or operated for dynamically controlling the overall or equivalent parasitic effects according to usage conditions or performance under demand. The usage conditions may comprise, for example, load conditions, switching frequency conditions, driver voltage/current, and/or input voltage which affect the power consumption of the power device. Other embodiments are described and claimed.

Abstract: Techniques related to a power module employing multiple power sub-modules are described. More specifically, an embodiment combines and controls multiple power sub-modules of varying characteristics to improve the overall efficiency of the power module across varying load currents, power outputs, input voltages, and other operating conditions. Moreover, the power module may employ an adaptive non-linear and non-uniform current/power sharing among its power sub-modules. Other embodiments are described and claimed.

Abstract: Techniques related to a power module employing multiple power sub-modules are described. More specifically, an embodiment combines and controls multiple power sub-modules of varying characteristics to improve the overall efficiency of the power module across varying load currents, power outputs, input voltages, and other operating conditions. Moreover, the power module may employ an adaptive non-linear and non-uniform current/power sharing among its power sub-modules. Other embodiments are described and claimed.

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Abstract: A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Abstract: A mechanism for automatically enabling and disabling clock signals includes a driver for providing a clock signal as an output, a gate coupled to the driver, and a sensing circuit coupled to both the output of the driver and to the gate. The sensing circuit provides a signal to the gate responsive to the output being in a first state. The gate then prevents the driver from driving the clock signal responsive to the signal from the sensing circuit. In one embodiment, a generator is coupled to the driver for providing a waveform to the driver. The driver then provides the clock signal based on this input waveform. Additionally, the gate is situated between the generator and the driver. The gate, based on the output of the sensing circuit, can then prevent the waveform from being provided to the driver.