Patents by Inventor Raviprakrash S. Rao

Raviprakrash S. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory having an ECC system
    Patent number: 8201033
    Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 12, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
  • Memory Having an ECC System
    Publication number: 20110258515
    Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
    Type: Application
    Filed: June 30, 2011
    Publication date: October 20, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
  • Memory having an ECC system
    Patent number: 7996734
    Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: August 9, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
  • Memory Having an ECC System
    Publication number: 20100281302
    Abstract: An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
    Type: Application
    Filed: July 9, 2010
    Publication date: November 4, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi
  • Memory having an ECC system
    Patent number: 7779334
    Abstract: An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Adrian Earle, Raviprakrash S. Rao, Vineet Joshi