Patents by Inventor Raviraj Raju

Raviraj Raju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230384975
    Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Disha Gundecha, Raviraj Raju
  • Patent number: 11829647
    Abstract: A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: November 28, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kalpit Bordia, Disha Gundecha, Raviraj Raju
  • Patent number: 11733914
    Abstract: A QLC based data storage device leverages a host memory buffer (HMB) to achieve QLC direct write that increases performance of the QLC data storage device and reducing or eliminating disadvantages associated with a QLC folding approach. In one example, the QLC based data storage device includes a controller configured to receive a request to write data to a non-volatile memory, determine whether the request is a sequential write operation, determine whether a HMB of the data storage device is enabled, determine whether a HMB allocation is successful for a quad-level cell direct write, and responsive to determining that the request is not the sequential write operation, the HMB of the data storage device is enabled, and the HMB allocation is successful for the quad-level cell direct write, perform a direct write operation in a quad-level cell block of the non-volatile memory.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 22, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Raviraj Raju, Sridhar Prudvirag Gunda
  • Publication number: 20230140773
    Abstract: A QLC based data storage device leverages a host memory buffer (HMB) to achieve QLC direct write that increases performance of the QLC data storage device and reducing or eliminating disadvantages associated with a QLC folding approach. In one example, the QLC based data storage device includes a controller configured to receive a request to write data to a non-volatile memory, determine whether the request is a sequential write operation, determine whether a HMB of the data storage device is enabled, determine whether a HMB allocation is successful for a quad-level cell direct write, and responsive to determining that the request is not the sequential write operation, the HMB of the data storage device is enabled, and the HMB allocation is successful for the quad-level cell direct write, perform a direct write operation in a quad-level cell block of the non-volatile memory.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Raviraj Raju, Sridhar Prudvirag Gunda