Patents by Inventor RAVISHANKAR KUMARASWAMY

RAVISHANKAR KUMARASWAMY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for dynamic and configurable L2/L3 data—plane in FPGA
    Patent number: 10044614
    Abstract: A system and method for providing multi-processor data plane architecture have been provided. The method comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units are selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, such as DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: August 7, 2018
    Assignee: TEJAS NETWORKS LIMITED
    Inventors: Vinayak Bhat, Likhit Kulkarni, Anuj Kumar Srivastava, Sachin Kashyap, Abhijit Das, Ravishankar Kumaraswamy
  • SYSTEM AND METHOD FOR DYNAMIC AND CONFIGURABLE L2/L3 DATA-PLANE IN FPGA
    Publication number: 20150281131
    Abstract: A system and method for providing multi-processor data plane architecture have been provided. The method comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units are selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, such as DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 1, 2015
    Inventors: VINAYAK BHAT, LIKHIT KULKARNI, ANUJ KUMAR SRIVASTAVA, SACHIN KASHYAP, ABHIJIT DAS, RAVISHANKAR KUMARASWAMY