Patents by Inventor Ravishankar Rao

Ravishankar Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11922220
    Abstract: Embodiments of systems, apparatuses and methods provide enhanced function as a service (FaaS) to users, e.g., computer developers and cloud service providers (CSPs). A computing system configured to provide such enhanced FaaS service include one or more controls architectural subsystems, software and orchestration subsystems, network and storage subsystems, and security subsystems. The computing system executes functions in response to events triggered by the users in an execution environment provided by the architectural subsystems, which represent an abstraction of execution management and shield the users from the burden of managing the execution. The software and orchestration subsystems allocate computing resources for the function execution by intelligently spinning up and down containers for function code with decreased instantiation latency and increased execution scalability while maintaining secured execution.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Mohammad R. Haghighat, Kshitij Doshi, Andrew J. Herdrich, Anup Mohan, Ravishankar R. Iyer, Mingqiu Sun, Krishna Bhuyan, Teck Joo Goh, Mohan J. Kumar, Michael Prinke, Michael Lemay, Leeor Peled, Jr-Shian Tsai, David M. Durham, Jeffrey D. Chamberlain, Vadim A. Sukhomlinov, Eric J. Dahlen, Sara Baghsorkhi, Harshad Sane, Areg Melik-Adamyan, Ravi Sahita, Dmitry Yurievich Babokin, Ian M. Steiner, Alexander Bachmutsky, Anil Rao, Mingwei Zhang, Nilesh K. Jain, Amin Firoozshahian, Baiju V. Patel, Wenyong Huang, Yeluri Raghuram
  • Patent number: 11017000
    Abstract: A method and system for identifying clinical trial sites is provided. The method includes receiving clinical trial data associated with a plurality of planned clinical trials. Portions of the clinical trial data are identified based on differing data sources. Relevant information is extracted from the portions. Socioeconomic data, demographics data, and epidemiological data are received and combined into a common format. Incorrect address data is corrected and the clinical trial data, socioeconomic data, demographics data, and epidemiological data are standardized. In response, an initial list is generated. The initial list includes associated principle investigators and clinical trial sites associated with planned clinical trials overlaid on the clinical trial data, the socioeconomic data, the demographics data, and the epidemiological data.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Timothy L. Dietlin, Abhinav N. Jain, Radhesh B. Nair, Ravishankar Rao
  • Patent number: 10740126
    Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao
  • Publication number: 20200012669
    Abstract: A method and system for identifying clinical trial sites is provided. The method includes receiving clinical trial data associated with a plurality of planned clinical trials. Portions of the clinical trial data are identified based on differing data sources. Relevant information is extracted from the portions. Socioeconomic data, demographics data, and epidemiological data are received and combined into a common format. Incorrect address data is corrected and the clinical trial data, socioeconomic data, demographics data, and epidemiological data are standardized. In response, an initial list is generated. The initial list includes associated principle investigators and clinical trial sites associated with planned clinical trials overlaid on the clinical trial data, the socioeconomic data, the demographics data, and the epidemiological data.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Timothy L. Dietlin, Abhinav N. Jain, Radhesh B. Nair, Ravishankar Rao
  • Patent number: 10515099
    Abstract: A method and system for identifying clinical trial sites is provided. The method includes receiving clinical trial data associated with a plurality of planned clinical trials. Portions of the clinical trial data are identified based on differing data sources. Relevant information is extracted from the portions. Socioeconomic data, demographics data, and epidemiological data are received and combined into a common format. Incorrect address data is corrected and the clinical trial data, socioeconomic data, demographics data, and epidemiological data are standardized. In response, an initial list is generated. The initial list includes associated principle investigators and clinical trial sites associated with planned clinical trials overlaid on the clinical trial data, the socioeconomic data, the demographics data, and the epidemiological data.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: December 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy L. Dietlin, Abhinav N. Jain, Radhesh B. Nair, Ravishankar Rao
  • Publication number: 20190370038
    Abstract: An apparatus and method for providing support for execution of optimized code. The apparatus includes a processor that is configured to convert guest code to native code and monitor access to an indicated memory address range associated with a read-only portion of the memory and to detect access to the indicated memory address range. The processor is further configured to raise an exception in response to memory access to the indicated memory address range and determine an access property of the indicated memory address range.
    Type: Application
    Filed: July 24, 2017
    Publication date: December 5, 2019
    Inventors: Micah VILLMOW, Kevin LAWTON, Ravishankar RAO, Mohammad A. ABDALLAH
  • Patent number: 10248570
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ravishankar Rao, Karthikeyan Avudaiyappan
  • Publication number: 20190056964
    Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 21, 2019
    Inventors: Mohammad Abdallah, Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao
  • Patent number: 10140138
    Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao
  • Publication number: 20180165206
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Application
    Filed: January 4, 2018
    Publication date: June 14, 2018
    Inventors: Mohammad Abdallah, Ravishankar Rao, Karthikeyan Avudaiyappan
  • Patent number: 9904625
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ravishankar Rao, Karthikeyan Avudaiyappan
  • Patent number: 9898412
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ravishankar Rao, Karthikeyan Avudaiyappan
  • Patent number: 9891915
    Abstract: A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Mohammad A. Abdallah, Ravishankar Rao
  • Publication number: 20170192906
    Abstract: A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.
    Type: Application
    Filed: January 17, 2017
    Publication date: July 6, 2017
    Inventors: Ravishankar RAO, Nishit SHAH
  • Patent number: 9606935
    Abstract: A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Ravishankar Rao, Nishit Shah
  • Publication number: 20160371188
    Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
    Type: Application
    Filed: September 6, 2016
    Publication date: December 22, 2016
    Inventors: Mohammad ABDALLAH, Ravishankar RAO, Karthikeyan AVUDAIYAPPAN
  • Publication number: 20160300040
    Abstract: A method and system for identifying clinical trial sites is provided. The method includes receiving clinical trial data associated with a plurality of planned clinical trials. Portions of the clinical trial data are identified based on differing data sources. Relevant information is extracted from the portions. Socioeconomic data, demographics data, and epidemiological data are received and combined into a common format. Incorrect address data is corrected and the clinical trial data, socioeconomic data, demographics data, and epidemiological data are standardized. In response, an initial list is generated. The initial list includes associated principle investigators and clinical trial sites associated with planned clinical trials overlaid on the clinical trial data, the socioeconomic data, the demographics data, and the epidemiological data.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 13, 2016
    Inventors: Timothy L. Dietlin, Abhinav N. Jain, Radhesh B. Nair, Ravishankar Rao
  • Patent number: 9454641
    Abstract: Systems and methods for modeling functional magnetic resonance image datasets using a multivariate auto-regressive model which captures temporal dynamics in the data, and creates a reduced representation of the dataset representative of functional connectivity of voxels with respect to brain activity. Raw spatio-temporal data is processed using a multivariate auto-regressive model, wherein coefficients in the model with high weights are retained as indices that best describe the full spatio-temporal data. When there are a relatively small number of temporal samples of the data, sparse regression techniques are used to build the model. The model coefficients are used to perform data processing functions such as indexing, prediction, and classification.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Guillermo A. Cecchi, Rahul Garg, Ravishankar Rao
  • Patent number: 9072496
    Abstract: Systems and methods for processing image data are provided. A computer implemented method for processing image data, comprises gathering 4-D image data from a subject, extracting time series data, and spatial and degree data of each voxel of the subject, deriving at least one feature from the time series data, deriving at least one feature from the spatial and degree data, combining the at least one feature from the time series data, and the at least one feature from the spatial and degree data to generate combined data, and inputting the combined data to a classifier, wherein the classifier outputs a classification based on the combined data.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: July 7, 2015
    Assignees: International Business Machines Corporation, University of Central Florida Research Foundation, Inc.
    Inventors: Ravishankar Rao, Soumyabrata Dey, Mubarak Shah, Solmaz Berkan
  • Publication number: 20140336998
    Abstract: Systems and methods for modeling functional magnetic resonance image datasets using a multivariate auto-regressive model which captures temporal dynamics in the data, and creates a reduced representation of the dataset representative of functional connectivity of voxels with respect to brain activity. Raw spatio-temporal data is processed using a multivariate auto-regressive model, wherein coefficients in the model with high weights are retained as indices that best describe the full spatio-temporal data. When there are a relatively small number of temporal samples of the data, sparse regression techniques are used to build the model. The model coefficients are used to perform data processing functions such as indexing, prediction, and classification.
    Type: Application
    Filed: July 25, 2014
    Publication date: November 13, 2014
    Inventors: Guillermo A. Cecchi, Rahul Garg, Ravishankar Rao