Abstract: Systems and methods for providing depth imaging using a CCD image sensor. In a method for visual imaging and depth imaging, steps include providing a CCD image sensor device arranged to receive light from an optical lens and having an array of pixels and corresponding pixel charge storage elements; providing a light source for transmitting light pulses responsive to a pulse control signal; providing timing signals to configure the CCD image sensor to collect and store charge from the pixel storage elements; and performing a depth calculation using a background charge, a reflected charge, and a depth charge collected in three frame periods for each pixel in the CCD image sensor. A system including a CCD image sensor for use with the embodiments is disclosed. Additional embodiments are disclosed.

Abstract: Systems and methods for providing depth imaging using a CCD image sensor. In a method for visual imaging and depth imaging, steps include providing a CCD image sensor device arranged to receive light from an optical lens and having an array of pixels and corresponding pixel charge storage elements; providing a light source for transmitting light pulses responsive to a pulse control signal; providing timing signals to configure the CCD image sensor to collect and store charge from the pixel storage elements; and performing a depth calculation using a background charge, a reflected charge, and a depth charge collected in three frame periods for each pixel in the CCD image sensor. A system including a CCD image sensor for use with the embodiments is disclosed. Additional embodiments are disclosed.

Abstract: Systems and methods for providing depth imaging using a CCD image sensor. In a method for visual imaging and depth imaging, steps include providing a CCD image sensor device arranged to receive light from an optical lens and having an array of pixels and corresponding pixel charge storage elements; providing a light source for transmitting light pulses responsive to a pulse control signal; providing timing signals to configure the CCD image sensor to collect and store charge from the pixel storage elements; and performing a depth calculation using a background charge, a reflected charge, and a depth charge collected in three frame periods for each pixel in the CCD image sensor. A system including a CCD image sensor for use with the embodiments is disclosed. Additional embodiments are disclosed.

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract: In a single wire communications interface embodiment, a single wire is coupled between a master device and at least one slave device, the master device configured for transmitting data words as serial data to and for receiving data words as serial data from the at least one slave device, and the at least one slave device configured for transmitting data words as serial data to and receiving data words as serial data from the master device; wherein prior to transmission of any data word on the single wire by one of the master device and the slave device, a sync pulse is first transmitted on the single wire. Integrated circuit embodiments for implementing the single wire communications interface, and method embodiments incorporating the single wire communications interface are disclosed. Additional embodiments are disclosed.

Abstract: Systems and methods for providing depth imaging using a CCD image sensor. In a method for visual imaging and depth imaging, steps include providing a CCD image sensor device arranged to receive light from an optical lens and having an array of pixels and corresponding pixel charge storage elements; providing a light source for transmitting light pulses responsive to a pulse control signal; providing timing signals to configure the CCD image sensor to collect and store charge from the pixel storage elements; and performing a depth calculation using a background charge, a reflected charge, and a depth charge collected in three frame periods for each pixel in the CCD image sensor. A system including a CCD image sensor for use with the embodiments is disclosed. Additional embodiments are disclosed.

Abstract: A switch provided between a first terminal and a second terminal with a varying cross terminal voltage. The switch contains two transistors, with the source terminal of the first transistor being coupled to the first terminal and a drain terminal of the second transistor being coupled to the second terminal. The gate terminal of the first transistor is coupled to the first terminal, the gate terminal of the second transistor is coupled to the second terminal, and the drain terminal of the first transistor is coupled to the source terminal of the second transistor. Due to such a topology, the cross-terminal voltage across the first and second terminals can be substantially higher than the voltage of the control signal indicating whether the switch is to be in on or off state.

Abstract: Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases while reducing the noise introduced into the amplified signal. A reference capacitor is coupled between an input terminal of the operational amplifier and a reference voltage in a first phase, and between the input terminal and a the reference voltage but with opposite polarity in the second phase.

Abstract: The present invention comprises a test set-up (20) and method of testing a correlated double sampling circuit (CDS) (24) by using a sinusoidal test signal (22) for measuring linearity. The present invention generates a sinusoidal signal with two accurate and known levels at two different time points, as an input to the CDS. The cosinusoidal output of the CDS is then processed using an ADC (60) and processor (62) to check the functionality and linearity of the CDS circuit under test.

Abstract: A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the feedback capacitor, the noise introduced by the stages is substantially reduced. Such switched capacitors can be used in analog to digital converters (ADC).

Abstract: Low voltage transistors are used in high voltage environment. The low voltage transistors may be used in the path of processing of a signal to increase the throughput performance. By using high voltage supply associated with the high voltage environment, a higher SNR may be attained. Various techniques are implemented to ensure that the low voltage transistors are not damaged by prolonged exposure to high voltages.

Abstract: A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using a second circuit portion to sample the bandwidth limited input signal. The first circuit portion and the second circuit portion may be implemented using separate components. In an alternative embodiment, bandwidth limiting is implemented by taking a difference of a sampled input signal from a sampled high frequency components of the input signal.

Abstract: The present invention comprises a test set-up (20) and method of testing a correlated double sampling circuit (CDS) (24) by using a sinusoidal test signal (22) for measuring linearity. The present invention generates a sinusoidal signal with two accurate and known levels at two different time points, as an input to the CDS. The cosinusoidal output of the CDS is then processed using an ADC (60) and processor (62) to check the functionality and linearity of the CDS circuit under test.

Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.

Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.