Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed prioritizing memory requests from core processors such that some memory transaction requests receive a higher priority than other memory transaction requests. In some embodiments, queue lengths and latency, frequency of core demand transaction prioritization and the like are monitored and prioritization throttled accordingly. Other embodiments may be described and/or claimed.

Abstract: Systems, apparatuses and methods may provide for technology that generates a first refresh request with respect to a first sub-channel in a dynamic random access memory (DRAM), generates a second refresh request with respect to a second sub-channel in the DRAM, wherein the first sub-channel and the second sub-channel share a channel boundary, and synchronizes the first refresh request with the second refresh request. In one example, the first sub-channel is associated with a first scheduling queue and the second sub-channel is associated with a second scheduling queue. The technology may also adaptively spread refresh commands over the refresh interval period, dynamically schedule refreshes based on bus efficiency and/or selectively issue opportunistic refreshes based on read/write traffic.