Patents by Inventor Rawan Naous
Rawan Naous has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11901004Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.Type: GrantFiled: April 8, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong
-
Publication number: 20240028869Abstract: A reconfigurable processing circuit of an AI accelerator and a method of operating the same are disclosed. In one aspect, the reconfigurable processing circuit includes a first memory configured to store an input activation state, a second memory configured to store a weight, a multiplier configured to multiply the weight and the input activation state and output a product, a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element, a third memory configured to store a first sum, a second mux configured to, based on a second selector, output the previous sum or the first sum, an adder configured to add the product and the previous sum or the first sum to output a second sum, and a third mux configured to, based on a third selector, output the second sum or the previous sum.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xiaoyu Sun, Rawan Naous, Murat Kerem Akarvardar
-
Publication number: 20230376273Abstract: A compute-in-memory device may include a Booth encoder configured to receive at least one input of first bits, a Booth decoder configured to receive at least one weight of second bits and to output a plurality of partial products of the at least one input and the at least one weight, an adder configured to add a first partial product of the plurality of the partial products and a second partial product of the plurality of partial products before the Booth decoder generates a third partial product of the plurality of the partial products and to generate a plurality of sums of partial products, and a carry-lookahead adder configured to add the plurality of sums of partial products and to generate a final sum.Type: ApplicationFiled: May 20, 2022Publication date: November 23, 2023Inventors: Rawan Naous, Kerem Akarvardar, Hidehiro Fujiwara, Haruki Mori, Mahmut Sinangil, Yu-Der Chih
-
Publication number: 20230367497Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xiaoyu Sun, Kerem Akarvardar, Rawan Naous
-
Publication number: 20230368014Abstract: A design method, an operating method and an electronic system are provided. The method comprises receiving a training dataset having a plurality of training data, wherein each training data is labeled to one of a plurality of classes; selecting at least one first class from the plurality of classes and establishing a first category having the at least one selected first class; training a first model with the training dataset, and using the at least one first class within the first category for verification; and implementing the first model on the accelerator.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kerem Akarvardar, Rawan Naous, Xiaoyu Sun
-
Publication number: 20230326525Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.Type: ApplicationFiled: April 8, 2022Publication date: October 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong
-
Publication number: 20230229922Abstract: A training method, an operating method and a memory system are provided. The operating method comprises using a first memory block of the memory system for computation; obtaining an aging condition of the memory system; determining whether the aging condition meets a predetermined aging condition; and when it is determined that the aging condition meets the predetermined aging condition, enabling the second memory block and using the first memory block and the second memory block for computation.Type: ApplicationFiled: January 17, 2022Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Xiaoyu Sun, Kerem Akarvardar, Rawan Naous
-
Publication number: 20230133360Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.Type: ApplicationFiled: May 26, 2022Publication date: May 4, 2023Inventors: Rawan Naous, Kerem Akarvardar, Mahmut Sinangil, Yu-Der Chih, Saman Adham, Nail Etkin Can Akkaya, Hidehiro Fujiwara, Yih Wang, Jonathan Tsung-Yung Chang
-
Publication number: 20230050279Abstract: An integrated circuit includes a first encoder, a compute in-memory (CIM) array and a de-encoder. The first encoder is configured to quantize a first received signal into a first signal. The first received signal has a first floating point number format. The first signal has an integer number format. The compute in-memory (CIM) array is coupled to the first encoder. The CIM array is configured to generate a CIM signal in response to at least the first signal. The CIM signal has the integer number format. The de-encoder is coupled to the CIM array, and is configured to generate a first output signal in response to the CIM signal. The first output signal has a second floating point number format.Type: ApplicationFiled: January 31, 2022Publication date: February 16, 2023Inventors: Rawan NAOUS, Kerem AKARVARDAR, Hidehiro FUJIWARA, Haruki MORI, Yu-Der CHIH, Mahmut SINANGIL, Yih WANG, Jonathan Tsung-Yung CHANG
-
Patent number: 11393527Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.Type: GrantFiled: July 7, 2020Date of Patent: July 19, 2022Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Rawan Naous, Khaled Nabil Salama
-
Publication number: 20200335162Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.Type: ApplicationFiled: July 7, 2020Publication date: October 22, 2020Inventors: Rawan NAOUS, Khaled Nabil SALAMA
-
Patent number: 10748609Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.Type: GrantFiled: April 10, 2018Date of Patent: August 18, 2020Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Rawan Naous, Khaled Nabil Salama
-
Publication number: 20200194066Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular It resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.Type: ApplicationFiled: April 10, 2018Publication date: June 18, 2020Inventors: Rawan NAOUS, Khaled Nabil SALAMA
-
Patent number: 10340001Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and—calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout.Type: GrantFiled: August 23, 2016Date of Patent: July 2, 2019Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Mohammed Affan Zidan, Hesham Omran, Rawan Naous, Ahmed Sultan Salem, Khaled Nabil Salama
-
Publication number: 20180233196Abstract: Methods are provided for mitigating problems caused by sneak-paths current during memory cell access in gateless arrays. Example methods contemplated herein utilize adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer memory system to address this sneak-paths problem. The method of the invention is a method for reading a target memory cell located at an intersection of a target row of a gateless array and a target column of the gateless array, the method comprising: —reading a value of the target memory cell; and —calculating an actual value of the target memory cell based on the read value of the memory cell and a component of the read value caused by sneak path current. Utilizing either an “initial bits” strategy or a “dummy bits” strategy in order to calculate the component of the read value caused by sneak path current, example embodiments significantly reduce the number of memory accesses pixel for an array readout.Type: ApplicationFiled: August 23, 2016Publication date: August 16, 2018Inventors: Mohammed Affan Zidan, Hesham Omran, Rawan Naous, Ahmed Sultan Salem, Khaled Nabil Salama