Patents by Inventor Ray A. Hill
Ray A. Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220253793Abstract: Various embodiments of systems and methods allow a tool inventory device and associated system. A user can retrieve and return tools and such interactions can be monitored by the system. The inventory device can be an add-on to a standalone tool cabinet and can provide this extra functionality. The inventory device can have a camera looking at the drawers and can use computer vision to determine when tools are retrieved and/or replaced.Type: ApplicationFiled: May 22, 2020Publication date: August 11, 2022Applicant: c/o PROKITS SOURCING COMPANYInventor: Ray HILL
-
Patent number: 8650834Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: GrantFiled: January 2, 2013Date of Patent: February 18, 2014Assignee: Masonite CorporationInventors: Geoffrey B. Hardwick, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Patent number: 8589926Abstract: A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved.Type: GrantFiled: May 7, 2009Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Jimmy Ray Hill, Bret Ronald Olszewski, Luc Rene Smolders, David Blair Whitworth
-
Patent number: 8341919Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: GrantFiled: August 16, 2011Date of Patent: January 1, 2013Assignee: Masonite CorporationInventors: Geoffrey B. Hardwick, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Publication number: 20120165761Abstract: A drug therapy elution system and method for treating blood vessels. The system includes an enclosed receptacle containing the drug therapy for treating the damaged blood vessel. The system also includes one or more conduits that permit elution of the drug therapy from the enclosed receptacle into the damaged blood vessel wall. The system also includes one or more fixation mechanisms that can secure the enclosed receptacle to the blood vessel wall.Type: ApplicationFiled: December 27, 2010Publication date: June 28, 2012Inventor: Ray Hill
-
Publication number: 20110296793Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: ApplicationFiled: August 16, 2011Publication date: December 8, 2011Inventors: Geoffrey B. HARDWICK, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Patent number: 7998382Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: GrantFiled: April 7, 2010Date of Patent: August 16, 2011Assignee: Masonite CorporationInventors: Geoffrey B. Hardwick, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Patent number: 7918024Abstract: A method for manufacturing a turbine nozzle assembly using a fixture includes providing a first position of the fixture, positioning at least one datum of the turbine nozzle assembly adjacent at least one datum location point on the fixture when the fixture is in the first position, coupling the turbine nozzle assembly to the fixture when the fixture is in the first position, rotating the fixture from the first position into a second position that facilitates manufacturing the turbine nozzle assembly, and performing a manufacturing process on the turbine nozzle assembly when the fixture is in the second position.Type: GrantFiled: January 20, 2006Date of Patent: April 5, 2011Assignee: General Electric CompanyInventors: Frank Delano Mooney, Jr., Gary Eugene Wheat, Timothy Riggs, Kenneth Ray Hill, Jr., Ronald Dale Edwards
-
Publication number: 20100287319Abstract: A method, system, and computer usable program product for adjusting processor utilization data in polling environments are provided in the illustrative embodiments. An amount of a computing resource consumed during polling performed by the polling application over a predetermined period is received at a processor in a data processing system from a polling application executing in the data processing system. The amount forms a polling amount of the computing resource. Using the polling amount of the computing resource, another amount of the computing resource consumed for performing meaningful task is determined. The other amount forms a work amount of the computing resource. Using the work amount of the computing resource, an adjusted utilization of the computing resource is computed over a utilization interval. The data of the adjusted utilization is saved.Type: ApplicationFiled: May 7, 2009Publication date: November 11, 2010Applicant: International Business Machines CorporationInventors: Jimmy Ray Hill, Bret Ronald Olszewski, Luc Rene Smolders, David Blair Whitworth
-
Publication number: 20100258979Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: ApplicationFiled: April 7, 2010Publication date: October 14, 2010Inventors: Geoffrey B. HARDWICK, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Patent number: 7695658Abstract: The present invention is directed to a method of forming a molded core component. A mat formed from cellulosic fiber and resin is provided. The mat is consolidated in a first press until the resin is substantially fully cured, and then removed from the first press. The consolidated mat is then placed in a second press having a mold cavity shaped to form at least one depression in at least one of the major surfaces. The consolidated mat is reformed in the second press to form a molded core component having at least one depression in at least one of the major surfaces. The molded core component has a variable density, preferably of between about 10 lbs/ft3 and 80 lbs/ft3.Type: GrantFiled: January 3, 2007Date of Patent: April 13, 2010Assignee: Masonite CorporationInventors: Geoffrey B. Hardwick, Henry M. Coghlan, John Peter Walsh, Allen Ray Hill
-
Patent number: 7338907Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.Type: GrantFiled: October 4, 2004Date of Patent: March 4, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Tingkai Li, Sheng Teng Hsu, Bruce D. Ulrich, Mark A. Burgholzer, Ray A. Hill
-
Publication number: 20060073706Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.Type: ApplicationFiled: October 4, 2004Publication date: April 6, 2006Inventors: Tingkai Li, Sheng Hsu, Bruce Ulrich, Mark Burgholzer, Ray Hill
-
Patent number: 6764625Abstract: A core component is molded to include surface depressions to compensate for varying widths and depths of the shell or framing of a building or structural member. The component includes two major surfaces defining respective front and rear sides of the component, and the rear side of the component is preferably the mirror image of the front side. The core component is preferably pre-formed and the surface layers are wetted to contain at least 2%, preferably about 4% to 20%, more moisture than at the thickness center of the mat to provide surfaces capable of adhesive coating for adherence to surrounding structural members, preferably two prefabricated molded doorskins. The core component is preferably made from a composite soft board material.Type: GrantFiled: March 6, 2002Date of Patent: July 20, 2004Assignee: Masonite CorporationInventors: John Peter Walsh, Geoffrey Brian Hardwick, Allen Ray Hill
-
Publication number: 20030224619Abstract: A method of low-temperature oxidation of a silicon substrate includes placing a silicon wafer in a vacuum chamber; maintaining the silicon wafer at a temperature of between about room temperature and 400° C.; introducing an oxidation gas in the vacuum chamber; dissociating the oxidation gas into O(1D) radical oxygen and irradiating the surface of the silicon wafer with a xenon excimer lamp generating light at a wavelength of about 172 nm to eject electrons from the surface of the silicon wafer and forming the reactive oxidizing species over the silicon wafer; and forming an oxide layer on at least a portion of the silicon wafer.Type: ApplicationFiled: June 4, 2002Publication date: December 4, 2003Inventors: Yoshi Ono, Ray Hill, Mark A. Burgholzer
-
Publication number: 20030168769Abstract: A core component is molded to include surface depressions to compensate for varying widths and depths of the shell or framing of a building or structural member. The component includes two major surfaces defining respective front and rear sides of the component, and the rear side of the component is preferably the mirror image of the front side. The core component is preferably pre-formed and the surface layers are wetted to contain at least 2%, preferably about 4% to 20%, more moisture than at the thickness center of the mat to provide surfaces capable of adhesive coating for adherence to surrounding structural members, preferably two prefabricated molded doorskins. The core component is preferably made from a composite soft board material.Type: ApplicationFiled: March 6, 2002Publication date: September 11, 2003Inventors: John Peter Walsh, Geoffrey Brian Hardwick, Allen Ray Hill
-
Patent number: 6150255Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.Type: GrantFiled: August 13, 1999Date of Patent: November 21, 2000Assignee: International Business Machines CorporationInventors: Francis Joseph Downes, Jr., Stephen Joseph Fuerniss, Gary Ray Hill, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla
-
Patent number: 5940729Abstract: According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface.The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.Type: GrantFiled: April 17, 1996Date of Patent: August 17, 1999Assignee: International Business Machines Corp.Inventors: Francis Joseph Downes, Jr., Stephen Joseph Fuerniss, Gary Ray Hill, Anthony Paul Ingraham, Voya Rista Markovich, Jaynal Abedin Molla
-
Patent number: 5672980Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.Type: GrantFiled: February 15, 1996Date of Patent: September 30, 1997Assignee: International Business Machines CorporationInventors: Richard Gordon Charlton, George Charles Correia, Mark Andrew Couture, Gary Ray Hill, Kibby Barth Horsford, Anthony Paul Ingraham, Michael David Lowell, Voya Rista Markovich, Gordon Charles Osborne, Jr., Mark Vincent Pierson
-
Patent number: 5659256Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.Type: GrantFiled: February 15, 1996Date of Patent: August 19, 1997Assignee: International Business Machines CorporationInventors: Richard Gordon Charlton, George Charles Correia, Mark Andrew Couture, Gary Ray Hill, Kibby Barth Horsford, Anthony Paul Ingraham, Michael David Lowell, Voya Rista Markovich, Gordon Charles Osborne, Jr., Mark Vincent Pierson