Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: A system and method for realizing a multi-camera system having two optical paths with a single processing path for the two optical paths. Such a multi-camera system typically includes a first image-capture device associated with a first optical train wherein the first image-capture device is typically pointed in a first direction (i.e., away from the user). The multi-camera system further includes a second image-capture device having a second optical train wherein the second image-capture device is typically pointed in a second direction (i.e., toward the user). The multi-camera system further includes a single processing block coupled to the first image-capture device and the second image-capture device. The processing block is typically operable to process image data captured at each image-capture device.

Abstract: An electronic circuit having built-in self testing capabilities for optimizing power consumption. Typically, the electronic circuit includes a component circuit that operates at some known or unknown optimal operating power level. Further, the electronic circuit includes a power supply coupled to the component circuit such that the power supply provides power to the component circuit. Further yet, the electronic circuit includes a test circuit coupled to the component circuit and coupled to the power supply. The test circuit is operable to monitor the power supplied to the component circuit and operable to control the power supply. In an iterative manner, the test circuit reduces the power supplied to the component circuit until the power supplied to the component circuit is operating at the optimal operating power level.

Abstract: A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sample is selected. Image signals from each pixel circuit in the selected row are routed to a different one of the plurality of column amplifiers when the APS image sensor is in the normal mode of operation. Image signals from a plurality of the pixel circuits in the selected row are routed to one of the plurality of column amplifiers when the APS image sensor is in the sub-sampling mode of operation.

Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: Compact CMOS pixel sensors containing three or four total transistors and four or five control lines provide a high percentage of sensor area for the photodiode that measures light intensity. The CMOS pixel sensors thus have good light sensitivity. The CMOS pixel sensors also provide active reset operations yielding low noise when resetting node voltages. The low transistor count is achieved using the same transistors during both reset operations and readout operation. Reversing the current direction through a pixel sensor during readout allows the row selection transistor to act as a buffer for a transistor having a gate coupled to the photodiode node.

Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: Compact CMOS pixel sensors containing three or four total transistors and four or five control lines provide a high percentage of sensor area for the photodiode that measures light intensity. The CMOS pixel sensors thus have good light sensitivity. The CMOS pixel sensors also provide active reset operations yielding low noise when resetting node voltages. The low transistor count is achieved using the same transistors during both reset operations and readout operation. Reversing the current direction through a pixel sensor during readout allows the row selection transistor to act as a buffer for a transistor having a gate coupled to the photodiode node.

Abstract: An active pixel sensor arrangement that provides sub-sampling and reset of all pixel cells after sub-sampling. In one embodiment, logic is provided between sampled and non-sampled rows to propagate reset signals to the non-sampled rows when the sampled rows are reset. In another embodiment, reset of non-sampled rows is implemented with control logic.

Abstract: A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sample is selected. Image signals from each pixel circuit in the selected row are routed to a different one of the plurality of column amplifiers when the APS image sensor is in the normal mode of operation. Image signals from a plurality of the pixel circuits in the selected row are routed to one of the plurality of column amplifiers when the APS image sensor is in the sub-sampling mode of operation.

Abstract: An active pixel sensor (APS) circuit which provides enhanced test and signal processing capabilities. APSs usually include pixel cells arranged in an array of rows and columns. Selectably enableable coupling conductors are provided between principal conductors in the array to permit a signal on one principal conductors to propagate to another principal conductors. The principal conductors include row, reset and column conductors. Signal propagation for testing purposes and for normal mode operation are disclosed.

Abstract: An ESD protection circuit for a BICMOS IC device protects NMOS transistors (Q2) of internal CMOS gates (G2) from ESD events at a high potential power rail (VCC). Specifically the ESD protection circuit protects NMOS pulldown transistors coupled between a pullup bipolar emitter follower transistor (Q5) and the low potential power rail (GND). A PMOS current control transistor (QPESD) is coupled with primary current path between the high potential power rail (VCC) and the bipolar emitter follower transistor (Q5) for controlling current flow through the emitter follower transistor. An RC time constant circuit (R10,C1) is coupled between the high potential power rail (VCC) and low potential power rail (GND). The RC time constant circuit is constructed with a time constant for following power up events but not for following the faster ESD events at the high potential power rail.

Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay.

Abstract: A translator circuit for converting from a first logic-level range to a second logic-level range, as is generally involved in the translation from an ECL stage to a CMOS stage. The translator includes a reference stage that provides a reference voltage that is coupled to the CMOS logic stage as well as the ECL logic stage. The ECL logic stage is indirectly coupled between a high potential power rail and a low potential power rail through a plurality of transistors. The CMOS stage is coupled to the ECL stage through two emitter-follower transistors. The CMOS stage uses current-mirroring techniques in combination with the isolated reference stage to effect a translation from the ECL logic level to the CMOS logic level. The CMOS stage also provides relatively fast propagation time which may be set, within certain limits, to a desired time.

Abstract: An output skew detection circuit detects and measures output skew tOSLH, tOSHL between multiple in phase common edge output signals propagated through a multiple signal driver circuit having n outputs. The output skew detection circuit senses common edge output skew across the n in phase output signals simultaneously and directly. A first logic gate has n inputs coupled to the n outputs, detects occurrence of either the first or last of the multiple common edge output signals, and generates a first skew detection edge signal at a first logic gate output. The first and last common edge output signals are the signals propagated with minimum and maximum propagation times tplhmin, tphlmin and tplhmax, tphlmax. A second logic gate has n inputs coupled to the n outputs in parallel with the first logic gate. The second logic gate detects occurrence of the other of the first and last of the multiple common edge output signals and generates a second skew detection edge signal at a second logic gate output.

Abstract: A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Abstract: A voltage controlled oscillator (VCO) operating as a variable length, variable delay, ring oscillator having a current starved inverter and an anti high-gain circuit for each stage. A VCO feedback signal is compared with a reference frequency obtained, for example, from a system crystal oscillator. A phase and frequency detector monitors these two input signals and issues "up" or "down" commands to a digital counter. This digital counter delivers select signals via a decoder and also drives a Digital to Analog Converter ("DAC"). The digital select signal from the counter chooses an operational stage from the multi-stage, tandem-connected VCO. A broadband operation for the VCO is achieved by overlapping the individual frequency ranges associated with each of the individual stages. The DAC moves the operation along each selected frequency range associated with a selected stage until a system lock between the VCO output and the crystal references is achieved.

Abstract: A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal.

Abstract: Circuit configurations are described for use with split lead leadframes and relatively isolated quiet and noisy power rails to reduce power rail noise and circuit noise. An octal register transceiver circuit incorporates a latch (300) coupled to relatively quiet power rails (42,44) and an output buffer circuit (400) having an input circuit coupled to the latch (300) and relatively quiet power rails (42,44). The output driver transistors (Q433,Q434) of the output buffer circuit (400) are coupled to the relatively noisy output power rails (52,54) to isolate the latch circuit from power rail noise and minimize erroneous operation of the latch. A DC Miller Killer circuit (450) is constructed with delay control components (D456,D457,R460) and an alternative discharge path (R458,D459) to reduce aggravation of power rail noise during operation of DCMK.

Abstract: To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe.