Abstract: A subscriber line interface circuit which includes a transient signal detector with temporal hysteresis. During steady state operation, the drive current for the subscriber loop allows the loop to respond to changes in loop conditions according to a steady state time constant of the loop filter. Upon detection of a line voltage transient which exceeds a predetermined threshold in either a positive or negative direction, the filter time constant is significantly reduced (e.g., 100:1) and held at such reduced value following the initial transient and for a predetermined time period after the line voltage has fallen back below such predetermined threshold. This allows the transient conditions to be fully compensated prior to resetting the filter time constant back from the lower transient value to the higher steady state value.

Abstract: Interactive internet activities are a very popular means for gathering information for business, personal, medical, entertainment and other purposes. Most internet interaction is asymmetrical in nature in that a client's requests for information are much smaller (in data size) than the resulting information delivered by the server. Although the client/internet link is inherently asymmetrical, there remains a great deal of interaction and overhead required between the client and the server that increases the bandwidth needs for the client's upstream request channel. There are many advantages to reducing this upstream traffic volume and thereby making the internet interaction even more asymmetrical. Such compression of request data could allow more clients to utilize a single upstream data path instead of separate paths.

Abstract: A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch.

Abstract: A RISC-based microcontroller is described which uses "split" data buses in the functional areas of the ALU and the I/O peripheral control interface. Also, the "Harvard" architecture is applied with separate buses for instructions and operational data which are stored and supplied from separate memories, i.e., an instruction memory and a data memory. This architecture allows to run the microcontroller with timing and clocking schemes of higher frequencies resulting in faster speed and higher processing rates in MIPS. The different functional components of the microcontroller can be placed on a single VLSI chip while other designs with much less on-chip functions are also conceivable.

Abstract: A grade stake driver includes a frame for supporting a hammer and a grade stake under the hammer. A shuttle secured to the hammer movably mounts onto the frame to connect the hammer to the frame. A hoist secured to the shuttle mounts onto the frame to permit the raising and lowering of the hammer. A receiver mounted on the frame outputs a control signal in response to a transmitted signal. A switch mounted on the frame transforms the control signal into an on/off signal. A relay mounted on the frame connects the hammer to a power source in response to the on/off signal, thereby effecting the driving of the grade stake.

Abstract: The prosthetic foot includes an extending forefoot and an extending heel which curve into arcing sections to be positioned in an overlapping and opposite fashion. A fastener securely fastens the forefoot and the heel to one another at a convergence of the arcing sections. The arcing sections define a receptacle for elements which limit the deflection of the forefoot and the heel. The preferred embodiment has a plurality of individual forefoot and heel members which readily accommodate uneven or angled terrain by individually flexing to conform to the terrain.

Abstract: The invention described herein is a method and apparatus for vein location. The apparatus includes a vein locating device composed an inflatable bladder attached between two covers and including a holding straps for attaching the device to a limb of a human patient. The method described herein sets for the steps of placing the apparatus on the limb of a human patient and inflating the device so as to constrict veins in a desired area so as to permit the location of a particular vein or veins.

Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory.

Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Abstract: A process for making yellow, basic azomethine dyes for paper, leather and textiles; the process being an improvement in the process of reacting an azo dye base precursor of the formula ##STR1## wherein A is phenyl or substituted phenyl, with dimethyl sulfate in solution, and in the presence of an acid-binding agent, the improvement comprising reacting dimethyl sulfate in a molar excess of from 100% to 300% per mole of precursor, in an aqueous solution having at least 30 weight percent water and from 2.0 to 3.5 moles of magnesium oxide (as the acid-binding agent) per mole of precursor.

Abstract: A process for making yellow, basic azomethine dyes for paper, leather and textiles, and concentrated, stable solutions thereof; the process being an improvement in the process of reacting an azo dye base precursor of the formula ##SPC1##Wherein A is phenyl or substituted phenyl, with dimethyl sulfate in solution, and in the presence of an acid-binding agent,THE IMPROVEMENT COMPRISING EMPLOYING AN AQUEOUS SOLUTION HAVING AT LEAST 30 WEIGHT PERCENT WATER, EMPLOYING DIMETHYL SULFATE IN A MOLAR EXCESS OF FROM 100% TO 300%, AND EMPLOYING FROM 2.0 TO 3.5 MOLES OF MAGNESIUM OXIDE AS THE ACID-BINDING AGENT PER MOLE OF PRECURSOR.