Patents by Inventor Ray Bloker

Ray Bloker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD AND CIRCUIT FOR REDUCING CURRENT SURGE
    Publication number: 20160139656
    Abstract: Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.
    Type: Application
    Filed: January 21, 2016
    Publication date: May 19, 2016
    Inventors: Bharath UPPUTURI, Bruce KAUFFMANN, Ray BLOKER
  • Method and circuit for reducing current surge
    Patent number: 9299394
    Abstract: Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 29, 2016
    Assignee: Broadcom Corporation
    Inventors: Bharath Upputuri, Bruce Kauffmann, Ray Bloker
  • METHOD AND CIRCUIT FOR REDUCING CURRENT SURGE
    Publication number: 20140097702
    Abstract: Systems and methods are provided for reducing surge current in power gated designs. In one aspect, a storage capacitor supplies a portion of the current used to power up a circuit. The storage capacitor may be charged from a power supply or other source. When the circuit is to be powered up, the circuit is connected to the power supply and the storage capacitor. As a result, current is supplied to the circuit from the power supply and the storage capacitor to power up the circuit. Because a portion of the current used to power up the circuit is supplied from the storage capacitor, the amount of current needed from the power supply to power up the circuit can be reduced, thereby reducing current surge through the power supply. The storage capacitor may be shared by multiple circuits.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Bharath UPPUTURI, Bruce KAUFFMANN, Ray BLOKER
  • Dynamic node keeper system and method
    Patent number: 7221189
    Abstract: The present invention system and method provides voltage level support for an output target signal (e.g., a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e.g., a read operation) of the output target signal.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: May 22, 2007
    Assignee: Transmeta Corporation
    Inventors: Ray Bloker, Parag Gupta
  • Dynamic node keeper system and method
    Patent number: 6940314
    Abstract: The present invention system and method provides voltage level support for an output target signal (e.g., a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e.g., a read operation) of the output target signal.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 6, 2005
    Assignee: Transmeta Corporation
    Inventors: Ray Bloker, Parag Gupta