Abstract: The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width CW and a depth CD, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

Abstract: The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width CW and a depth CD, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

Abstract: An electronic memory device and a method of manipulating the electronic memory device. The electronic memory device includes a plurality of basic memory blocks connected together with a modular structure, wherein each of the basic memory blocks includes a plurality lookup tables (LUT) arranged to operate as an memory element for storing a plurality of bits of logic levels; and a plurality of registers each pairing up with a respective lookup table in the basic memory blocks; wherein the plurality of pairs of lookup tables and registers combine to form a pipelining memory structure.

Abstract: An electronic memory device and a method of manipulating the electronic memory device. The electronic memory device includes a plurality of basic memory blocks connected together with a modular structure, wherein each of the basic memory blocks includes a plurality lookup tables (LUT) arranged to operate as an memory element for storing a plurality of bits of logic levels; and a plurality of registers each pairing up with a respective lookup table in the basic memory blocks; wherein the plurality of pairs of lookup tables and registers combine to form a pipelining memory structure.