Abstract: A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a “tunnel oxide” layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.

Abstract: A method of patterning a metal line and removing the polymer layer that forms on the metal lines sidewalls in an important post etch-polymer removal step (e.g., step 4). A semiconductor structure and an overlying dielectric layer, a first barrier layer, a metal layer; a second barrier layer and resist pattern are provided. A four step etch process is performed in sequence in the same etch chamber. In a first etch step (A), we etch through the second barrier layer using a B and Cl containing gas and a Cl containing gas in a reactive ion etch to form a first polymer layer over the sidewall of the second barrier layer. In a second etch step (B), the metal layer is etched exposing the first barrier layer to form a second polymer over the first polymer and the sidewall of the metal layer; the second etch step performed using a B and Cl containing gas and a Cl containing gas. In a third etch step (C), the first barrier layer is etched to form a third polymer layer over the first and second polymer layers.

Abstract: An apparatus is provided for treating a wafer under fabrication with an erosive plasma, in a contamination controlled environment. The apparatus includes a chamber for containing the wafer to be treated by the plasma, and for isolating the wafer from contaminants external to the chamber during treatment. The chamber also includes one or more plasma erosion resistive screws. Each screw has a shaft secured within the chamber so that the shaft is unexposed to the plasma, and a raised head which is integral with, and made of the same material as, the shaft. The head has a continuous, surface shape with a reduced number of edges so as to reduce the accumulation of charge thereon, thereby resisting erosion by the plasma.

Abstract: A plasma erosion resistive clamping ring is provided for clamping a wafer in a plasma treatment chamber. The plasma erosion resistive clamping ring comprises a ring and one or more tips secured to, and mutually spaced apart about, a circumference of the ring. Each of the tips projects away from the ring, in a radial direction, towards an interior of the ring. Each tip has plural side surfaces that taper to, and meet, a single, continuous surface of rotation. The surface of rotation is located in the interior of the ring at a location of the tip which is radially most distant from the ring. The meeting of the tapered sides at the single continuous surface of rotation has a cross-section, taken in a plane of the ring, as follows. The cross-section comprises first and second line segments, on lines that intersect at an acute angle, and an arc of a convex ellipse, that begins at an end of the first line segment most distant from the ring, and ends at an end of the second line segment most distant from the ring.

Abstract: A method and resulting integrated circuit device (100) such as a flash memory device and resulting cell. The method includes a step of providing a substrate (115), which has an active region overlying a thin layer of dielectric material (113). The method uses a step of forming a floating gate layer (107) overlying the thin layer of dielectric material (113), which is commonly termed a "tunnel oxide" layer, but is not limited to such a layer or material. The floating gate layer (107) has novel geometric features including slant edges (121), which extend to the dielectric material (123). The slant edges (121) create a smaller geometric area for the tunnel oxide region relative to the area between the floating gate layer and the control gate layer.