Abstract: Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Abstract: Processing circuitry includes a selectively powered domain having a communications interface to communicate with power management circuitry via a bus in accordance with a bus protocol, and a processing core to control the communications interface, wherein the selectively powered domain is not powered when the processing circuitry is operating in any one of multiple low power modes. The processing circuitry also includes an always on power domain having a set of pins to communicate a set of handshake signals with the power management circuitry and a power management sequencer to control power mode transitions of the processing circuitry. When the processing circuitry is operating in one of the multiple low power modes such that the communications interface and the processing core are not powered, the power management sequencer generates a signature on the set of handshake signals to control power mode transitions from one of the multiple low power modes.

Abstract: A system comprising a real time clock, RTC, and a processor configured to execute a secure application to provide a secure clock and configured to operate in a first low-power-mode and a first normal-mode, and a non-secure application configured to perform a clock modification procedure and configured to operate in a second low-power-mode and a second normal-mode, the system configured to perform a secure clock initialisation procedure comprising obtaining a record of a current time from the RTC based on a transition from the first low-power-mode to the first normal-mode, wherein the secure application is configured to perform a clock update procedure including updating the RTC with a secure record of the current time and wherein the system is further configured to prevent performing the clock modification procedure after the clock update procedure has been performed.

Abstract: Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Abstract: A device has a cache memory for temporarily storing contents of a buffer memory. The device has a mirror unit coupled between the cache memory and the buffer memory. The mirror unit is arranged for providing at least two buffer mirrors at respective different buffer mirror address ranges in the main address range by adapting the memory addressing. Due to the virtual mirrors data on a respective address in any of the respective different buffer mirror address ranges is the data of the buffer memory at a corresponding address in the buffer address range. The device enables processing of a subsequent set of data in the buffer memory via the cache memory without invalidating the cache by switching to a different buffer mirror.

Abstract: A memory controller includes a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data, a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information, at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme, and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.

Abstract: The present application relates to a memory controller and a method of operating thereof. The memory controller comprises a transaction interface arranged to be coupled to a transaction interconnect to receive a write transaction comprising write data; a mode controller arranged to obtain context information and to select a data protection scheme out of a plurality of data protection schemes based on the obtained context information; at least one data protection module to apply the selected data protection scheme by generating one or more protection code sequences from at least the write data in accordance with the selected data protection scheme; and a physical memory interface coupled to at least one memory device to store the write data and the one or more protection code sequences in the at least one memory device.

Abstract: In a system on chip SoC, a memory control unit connected between the memory unit and the processing unit controls access to the memory unit. An update request received or generated by the processing unit triggers an update operation which comprises appending an update enabling record to a sequence of update records in the log region, writing new program code to the memory unit, and appending an update completion record to a sequence of update records. Write access to the log region is disabled if a fault is detected in the SoC during the update operation.

Abstract: The present invention relates to the synchronization of an internal combustion, four-stroke engine during engine startup. The engine comprises a number of cylinders with pistons linked to a crankshaft, means to provide a series of pulses on each cycle of the engine, and an engine management system that includes: a memory; means to determine the engine cycle after the engine is cranked; and means to count thereafter the series of pulses until the engine comes to a stop in order to determine the engine cycle of the engine when subsequently stopped so that data representative of the engine cycle may be stored in the memory. According to one aspect of the invention, the means to determine the engine cycle after the engine is cranked is a means to determine the engine cycle during running of the engine.