Patents by Inventor Ray-Chi Chang

Ray-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11567882
    Abstract: A method for delivering multiple write commands is provided. The method includes: encoding data to be written and corresponding addresses in the multiple write commands to obtain encoded data and an encoded address, wherein the addresses are not sequential; generating a virtual burst write command according to the encoded data and the encoded addresses; and transmitting a virtual burst-mode start indicator and the virtual burst write command through a serial bus.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: January 31, 2023
    Assignee: Himax Imaging Limited
    Inventors: Ray Chi Chang, Chih-Yen Yang
  • Publication number: 20220138121
    Abstract: A method for delivering multiple write commands is provided. The method includes: encoding data to be written and corresponding addresses in the multiple write commands to obtain encoded data and an encoded address, wherein the addresses are not sequential; generating a virtual burst write command according to the encoded data and the encoded addresses; and transmitting a virtual burst-mode start indicator and the virtual burst write command through a serial bus.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Inventors: Ray Chi Chang, Chih-Yen Yang
  • Patent number: 9503666
    Abstract: An image sensor includes readout circuits coupled to read out integrated light signals from pixels via bitlines respectively. Each readout circuit includes a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC). At least two pixels of a row share a bitline and an associated readout circuit. The ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 22, 2016
    Assignee: HIMAX IMAGING LIMITED
    Inventors: Ping-Hung Yin, Jia-Shyang Wang, Satya Narayan Mishra, Amit Mittra, Ray-Chi Chang
  • Publication number: 20160065872
    Abstract: An image sensor includes readout circuits coupled to read out integrated light signals from pixels via bitlines respectively. Each readout circuit includes a correlated double sampling (CDS) circuit, followed by an analog-to-digital converter (ADC). At least two pixels of a row share a bitline and an associated readout circuit. The ADC operates concurrently with the CDS circuit, such that their operating periods are substantially overlapped with each other.
    Type: Application
    Filed: January 22, 2015
    Publication date: March 3, 2016
    Inventors: PING-HUNG YIN, Jia-Shyang Wang, Satya Narayan Mishra, Amit Mittra, Ray-Chi Chang
  • Patent number: 9264632
    Abstract: A method of adaptively reducing power consumption in an image sensor includes using an electronic rolling shutter to reset pixels of the image sensor row by row. Signal charges are read out from the pixels row by row, followed by obtaining an integration time and a frame height. A power-saving signal is generated when the integration time is substantially greater than the frame height, and at least a circuitry that is not required to operate during an active period of the power-saving signal is turned off.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 16, 2016
    Assignee: Himax Imaging Limited
    Inventors: Ping-Hung Yin, Amit Mittra, Jia-Shyang Wang, Ray-Chi Chang
  • Publication number: 20160044256
    Abstract: A method of adaptively reducing power consumption in an image sensor includes using an electronic rolling shutter to reset pixels of the image sensor row by row. Signal charges are read out from the pixels row by row, followed by obtaining an integration time and a frame height. A power-saving signal is generated when the integration time is substantially greater than the frame height, and at least a circuitry that is not required to operate during an active period of the power-saving signal is turned off.
    Type: Application
    Filed: September 26, 2014
    Publication date: February 11, 2016
    Inventors: PING-HUNG YIN, Amit Mittra, Jia-Shyang Wang, Ray-Chi Chang
  • Patent number: 8218038
    Abstract: Multi-phase black level calibration (BLC) methods and systems are generally disclosed. According to one embodiment of the present invention, an image sensor comprises a pixel sensor array, a timing generator, and a front-end processing block. The front-end processing block also includes a first summing junction, a first BLC block, and a second BLC block. According to a first timing signal from the timing generator, the first BLC block is configured to iteratively generate a first calibration signal in a first phase based on a first set of adjusted black level signals associated with a first set of black pixels, a changing accumulator step, and a predetermined condition associated with a first target black level. According to a second timing signal from the timing generator, the second BLC block is configured to generate a second calibration signal for a second summing junction to apply to an image signal associated with one or more active pixels in the frame in a second phase.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: July 10, 2012
    Assignee: Himax Imaging, Inc.
    Inventors: Nguyen Dong, Amit Mittra, Ray-Chi Chang
  • Publication number: 20110141291
    Abstract: Multi-phase black level calibration (BLC) methods and systems are generally disclosed. According to one embodiment of the present invention, an image sensor comprises a pixel sensor array, a timing generator, and a front-end processing block. The front-end processing block also includes a first summing junction, a first BLC block, and a second BLC block. According to a first timing signal from the timing generator, the first BLC block is configured to iteratively generate a first calibration signal in a first phase based on a first set of adjusted black level signals associated with a first set of black pixels, a changing accumulator step, and a predetermined condition associated with a first target black level. According to a second timing signal from the timing generator, the second BLC block is configured to generate a second calibration signal for a second summing junction to apply to an image signal associated with one or more active pixels in the frame in a second phase.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: HIMAX IMAGING, INC.
    Inventors: Nguyen DONG, Amit MITTRA, Ray-Chi CHANG