Abstract: A method of forming micro-pore structures or trench structures on a surface of a silicon wafer substrate comprises (A) forming at least a noble-metal alloy particle on the surface of the silicon wafer substrate; and (B) then followed by employing a chemical wet etching on the surface of the silicon wafer substrate. During the processes, noble-metal alloy particle is used to catalyze the oxidation of the silicon wafer substrate surface in contact therewith, and an etchant is used to simultaneous etch the silicon dioxide to result in local micro-etching at the surface of the silicon wafer substrate, thereby forming micro-pore structures or trench structures on the surface of the silicon wafer substrate. The method increases the power conversion efficiency of the solar cells and reduces the manufacturing costs so as to increase the production benefits of the solar cells.

Abstract: A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a second silicon layer is located below the first silicon layer and the buried oxide area.

Abstract: A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having a second predetermined depth greater than the first predetermined depth, and a ground layer connected to the active device layer and the oxide region. The SOI structure further has a first silicon-based wafer and a second wafer. Both wafers are bonded together by wafer bonding. At least two different active device layer thicknesses exist to meet requirements of a wide variety of SOI devices placed thereon, with the setting of the oxide region filled with thermal oxide or other oxide variations.

Abstract: A package module of an IC device comprises a substrate, at least one semiconductor device, and an interconnected layer. The substrate has a first surface and a second surface, wherein the substrate further contains a plurality of metal plugs, which penetrate the substrate and connect the first surface and the second surface. The semiconductor device is located on the first surface of the substrate, wherein the semiconductor device contains a plurality of metal pads, each of which is connected to one of the metal plugs. The interconnected layer is formed on the second surface of the substrate, wherein the interconnected layer is comprised of a plurality of metal circuits, a plurality of land pads, and a plurality of via pads, wherein each of the metal plugs is connected to one of the metal circuits.

Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.

Abstract: An adapter assembly is provided for adapting an LGA packaged IC to a PGA socket. The adapter assembly comprises a package body with a plurality of through holes, and a plurality of pins received in the through holes and each having a spring end and an insertion end. The spring end of the pin abuts against an electric contact land of the LGA packaged IC and the insertion end of the pin is inserted into the PGA socket, whereby the LGA packaged IC is in electrical connection to the PGA socket.

Abstract: An SOI single crystalline chip structure includes an active device layer for having at least one SOI device placed thereon, a buried oxide layer under the active device layer, a metal layer under the buried oxide layer, and a silicon substrate under the metal layer. At least one through hole passing through the buried oxide layer is disposed at a first predetermined position of the buried oxide layer, and at least one concave hole not passing through the buried oxide layer is disposed at a second predetermined position of the bottom surface of the buried oxide layer.

Abstract: A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having a second predetermined depth greater than the first predetermined depth, and a ground layer connected to the active device layer and the oxide region. The SOI structure further has a first silicon-based wafer and a second wafer. Both wafers are bonded together by wafer bonding. At least two different active device layer thicknesses exist to meet requirements of a wide variety of SOI devices placed thereon, with the setting of the oxide region filled with thermal oxide or other oxide variations.

Abstract: A socket structure for grid array (GA) Packages, mainly comprises the flexible chassis assembly, the frame, the first hinge cover lid and the second hinge cover lid. The flexible chassis assembly comprises the silicon rubber pad, the inner base plate, the flex-board, two solder mask layers, bumps and solder balls. The flex-board, encompassing the silicon rubber pad and the inner base plate, is used for electrical contacts. Also, the first hinge cover lid is situated and pivoting on the frame by a first hinge pin and a second hinge pin; the second hinge cover lid is situated and pivoting on the frame by a third hinge pin and a fourth hinge pin. By pressing the first hinge cover lid and the second hinge cover lid downward, the hinge pads thereon contact with the substrate of the package and snap the package firm in place. In this invention, the package with pre-attached heat sink can be easily placed into the socket.

Abstract: A package module of an IC device comprises a substrate, at least one semiconductor device, and an interconnected layer. The substrate has a first surface and a second surface, wherein the substrate further contains a plurality of metal plugs, which penetrate the substrate and connect the first surface and the second surface. The semiconductor device is located on the first surface of the substrate, wherein the semiconductor device contains a plurality of metal pads, each of which is connected to one of the metal plugs. The interconnected layer is formed on the second surface of the substrate, wherein the interconnected layer is comprised of a plurality of metal circuits, a plurality of land pads, and a plurality of via pads, wherein each of the metal plugs is connected to one of the metal circuits.

Abstract: An elastomer interposer employed between a package and a printed circuit board and the method of manufacturing the same are disclosed. The elastomer interposer includes an elastomer, a plurality of conductive wires, Cu pads, solder resistant blocks and Ni/Au plated pads. The elastomer has two contact surfaces. The conductive wires are arranged inside the elastomer at a certain interval and tilted toward one of the contact surfaces with an inclined angle. The Cu pads are formed on both of the surfaces at a space, and electrically connected to the corresponding conductive wires. Also, the Ni/Au plated pads are formed over the Cu pads.

Abstract: A SOI (silicon on insulator) single crystalline chip structure is provided. The SOI chip structure has a first silicon layer for at least one SOI device to be placed thereon, at least one buried oxide area with a predetermined depth placed at a predetermined position of the first silicon layer in order to enable the first silicon layer to have at least two different silicon layer thicknesses. The buried oxide area is filled with a silicon oxide material serving as an insulating area, and a second silicon layer is located below the first silicon layer and the buried oxide area.

Abstract: An adapter assembly is provided for adapting an LGA packaged IC to a PGA socket. The adapter assembly comprises a package body with a plurality of through holes, and a plurality of pins received in the through holes and each having a spring end and an insertion end. The spring end of the pin abuts against an electric contact land of the LGA packaged IC and the insertion end of the pin is inserted into the PGA socket, whereby the LGA packaged IC is in electrical connection to the PGA socket.

Abstract: A socket structure for grid array (GA) packages, mainly comprises the flexible chassis assembly, the frame, the first hinge cover lid and the second hinge cover lid. The flexible chassis assembly comprises the silicon rubber pad, the inner base plate, the flex-board, two solder mask layers, bumps and solder balls. The flex-board, encompassing the silicon rubber pad and the inner base plate, is used for electrical contacts. By pressing the first hinge cover lid and the second hinge cover lid downward, the hinge pads thereon contact with the substrate of the package and snap the package firm in place. In this invention, the package with pre-attached heat sink can be easily placed into the socket.

Abstract: A socket structure for grid array (GA) Packages, mainly comprises the assembly of flexible chassis, the frame, the first hinge cover lid and the second hinge cover lid. The assembly of flexible chassis comprises the silicon rubber pad, the inner base plate and the flex-board, in which the flex-board, encompassing the silicon rubber pad and the inner base plate, is used for electrical contacts. By pressing the first hinge cover lid and the second hinge cover lid downward, the hinge pads thereon contact with the substrate of the package and snap the package firm in place. In this invention, the package with pre-attached heat sink can be easily placed into the socket.

Abstract: A flip-chip package module consists of a semiconductor chip, a heat sink plate, a dielectric layer and a metal interconnect layer. The semiconductor chip has a positive side with a plurality of die pads located thereon and a back side for mounting onto the heat sink plate. The dielectric layer is formed by depositing on the surface of the inner heat sink plate and encases the semiconductor chip therein. The metal interconnect layer is formed on the surface of the dielectric layer and includes a plurality of metal conductive wires. Each of the metal conductive wires connects to one of the die pads of the semiconductor chip through a via.

Abstract: A package module of an IC device comprises a substrate, at least one semiconductor device, and an interconnected layer. The substrate has a first surface and a second surface, wherein the substrate further contains a plurality of metal plugs, which penetrate the substrate and connect the first surface and the second surface. The semiconductor device is located on the first surface of the substrate, wherein the semiconductor device contains a plurality of metal pads, each of which is connected to one of the metal plugs. The interconnected layer is formed on the second surface of the substrate, wherein the interconnected layer is comprised of a plurality of metal circuits, a plurality of land pads, and a plurality of via pads, wherein each of the metal plugs is connected to one of the metal circuits.

Abstract: An elastomer interposer employed between a package and a printed circuit board and the method of manufacturing the same are disclosed. The elastomer interposer includes an elastomer, a plurality of conductive wires, Cu pads, solder resistant blocks and Ni/Au plated pads. The elastomer has two contact surfaces. The conductive wires are arranged inside the elastomer at a certain interval and tilted toward one of the contact surfaces with an inclined angle. The Cu pads are formed on both of the surfaces at a space, and electrically connected to the corresponding conductive wires. Also, the Ni/Au plated pads are formed over the Cu pads.

Abstract: A metal pad of a semiconductor element is disposed in an opening of a passivation layer of the semiconductor element and is connected to a metal interconnect layer of the semiconductor element through a plurality of metal plugs. The metal pad comprises a first aluminum alloy layer, a laser stop layer and a second aluminum alloy layer. The first aluminum alloy layer is disposed above the metal plugs; the laser stop layer is disposed on the upper surface of the first aluminum alloy layer and is made of a metal having a high melting point and a high laser reflection coefficient and has a thickness between 500 Å and 5000 Å; and the second aluminum alloy layer is disposed on the upper surface of the laser stop layer and has a thickness between 1000 Åand 20000 Å.

Abstract: An organic substrate and a heat spreader are separately made, and are then combined with a partially cured liquid-type adhesive layer. In making the organic substrate, a solder mask and a cavity as a pocket for an IC die are first formed on one side of an organic substrate. A pre-treatment process is performed to a copper layer on the opposite side of the organic substrate. A black ink layer is layered on one side of the heat spreader, and a second black ink layer is formed within a predetermined area on its opposite side. The predetermined area is reserved for positioning the IC die, and has a plurality of heat dissipating pads. A liquid-type adhesive printing process and a partial curing process are performed, which forms a solidified liquid-type adhesive layer outside of the predetermined area. The organic substrate is then laminated to the Cu heat spreader under high temperatures. Finally, a Ni/Au layer is plated onto a plurality of conductive pads and heat dissipating pads of the substrate.