Abstract: Provided herein are IL-21 prodrugs and methods of making and using thereof for stimulating the immune system, or treating cancer or an infectious disease.

Abstract: An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A novel method, which is suitable to substantially reduce the presence of oxygen micro-bubbles in an electroplating bath solution, is disclosed. The method includes the addition of aerobic bacteria to the electroplating bath solution to consume oxygen in the solution. Reduction of the oxygen content in the electroplating bath solution prevents oxygen micro-bubbles from forming in the solution and becoming trapped between the solution and the surface of a metal seed layer on a substrate to block the electroplating of a metal film onto the seed layer. Consequently, the presence of surface pits and other structural defects in the surface of the electroplated metal film is substantially reduced.

Abstract: An apparatus and method for preventing the peeling of electroplated metal from a wafer, is disclosed. The apparatus includes a seed layer detector system having a light source and a reflectivity detector. According to the method, the light source emits a beam of light onto a wafer and the reflectivity detector receives the light reflected from the wafer. The reflectivity of the wafer surface is measured to determine the presence or absence of a seed layer on the wafer, as well as whether the seed layer has a minimum thickness for optimum electroplating of a metal onto the seed layer.

Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.

Abstract: A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Abstract: A wafer cleaning system is provided. The wafer cleaning system comprises a first brush, a second brush, a brush motor, and a controller. The second brush is positioned parallel to the first brush. The brush motor moves at least one of the first and second brushes from a first position to a second position according to a driving current of the brush motor.

Abstract: A method for filling a structure using electrochemical deposition includes a barrier layer and a seed layer being deposited on one or more surfaces of the structure. Metal is electrochemically deposited to fill the structure in an electrochemical plating cell, wherein the electroplating surface of the substrate is tilted and rotated during electrochemical deposition.

Abstract: A method of electroplating conductive material on semiconductor wafers improves deposited film quality by providing greater control over the formation of the film grain structure. Better grain size control is achieved by applying a continuous DC plating current to the wafer which avoids sharp discontinuities in the current as the applied current is increased in successive stages during a plating cycle. Current discontinuities are avoided by gradually increasing the current in a ramp-like fashion between the successive plating stages.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A method for forming a microelectronic layer while employing a sputtering method employs a reactor chamber. A sputtering target and a substrate are positioned within the reactor chamber, along with a sputtering target heater at a side of sputtering target opposite the substrate. At least one of: (1) a heater to sputtering target distance; (2) sputtering power; (3) deposition time; and (4) sputtering gas flow rate, is controlled in accord with a pre-determined function of sputtering target lifetime to provide enhanced uniformity of the deposited layer.

Abstract: A disassembling device for separating a pedestal, a ceramic element and a base from an electrostatic chuck assembly. The base has a first end surface and a second end surface. The ceramic element is disposed on the first end surface. The pedestal is disposed on the ceramic element. The disassembling device includes a main body and at least one pushing element. The main body is disposed on the second end surface and has a through hole. The at least one pushing element penetrates the through hole and pushes against the ceramic element and pedestal to separate the ceramic element and pedestal from the first end surface of the base.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer-that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A thrust pad assembly which is capable of reducing the quantity of metal electroplated onto the edge region of a substrate to eliminate or reduce the need for edge bevel cleaning or removal of excess metal from the substrate after the electroplating process. The thrust pad assembly includes an air platen through which air is applied at variable pressures to the central and edge regions, respectively, of a thrust pad. The thrust pad applies pressure to a contact ring connected to an electroplating voltage source. The contact ring applies relatively less pressure to the edge region than to the central region of the substrate, thereby reducing the ohmic contact.

Abstract: A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Abstract: A disassembling device for separating a pedestal, a ceramic element and a base from an electrostatic chuck assembly. The base has a first end surface and a second end surface. The ceramic element is disposed on the first end surface. The pedestal is disposed on the ceramic element. The disassembling device includes a main body and at least one pushing element. The main body is disposed on the second end surface and has a through hole. The at least one pushing element penetrates the through hole and pushes against the ceramic element and pedestal to separate the ceramic element and pedestal from the first end surface of the base.

Abstract: A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2?t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)?GD2 for the second copper layer.