Abstract: An adaptive encoder (10) provides a fixed upper limit on the number of consecutively transmitted data bits at a particular data bit location of a data word having a common logic value. A coder circuit (44) provides prioritization for a storage comparator register (102) to determine when data in a data channel (32) should be complemented. An invert circuit (58) complements the data in the data channel (32) when an upper limit of consecutive transmitted data bits have common logic values.

Abstract: A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

Abstract: A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.

Abstract: The present invention provides an output signal whose pulse width may be adjusted with respect to the pulse width of an incoming input signal. In particular, a plurality of signals is generated in response to the input signal. One of the plurality of signals is selected for controlling when the output signal transitions from a first logic state to a second logic state, and one of the plurality of signals is selected for controlling when the output signal transitions from a second logic state to a first logic state wherein the output signal has a pulse width being a function of the selection of the plurality of signals.

Abstract: Binary current signals are differentiated to produce pulses indicative of the front and rear edges. The pulses are amplified and utilized in a latch to regenerate binary voltage signals which are amplified replicas of the input signals. Because of the input differentiator the sensitivity of the circuit remains high while the latched output makes the circuit burst mode ready.

Abstract: A circuit and method for providing phase synchronization between an ECL output signal and a TTL or CMOS output signal has been provided. The circuit includes phase locked loops (20, 24) to make the difference of delays through an ECL-TTL/CMOS translation path with that of a straight ECL path irrelevant. As a result, in order to achieve phase synchronization between an ECL signal and a TTL/CMOS signal, one only needs to match the propagation delay of a delay component (22) to that of a TTL/CMOS-ECL translator (26) as opposed to a delay component and an ECL-TTL/CMOS translator.

Abstract: A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.

Abstract: An ECL to TTL translator converts a signal from ECL logic levels to TTL compatible logic levels without introducing current spikes in the output signal during logic translations. The ECL input signal is transformed into first and second differentially related currents which develop first and second voltages for biasing first and second switching circuits which in turn generate first and second complementary control signals. The sum total of the differentially related currents are limited to a predetermined magnitude blocking simultaneously assertion of the control signals. An output stage includes an upper and lower transistors each responsive to the first and second control signal respectively for developing a TTL high and TTL low output signal. The first and second switching circuits inhibit simultaneous conduction of the upper and lower transistors of the output stage preventing undesirable current spikes in the output signal thereof.

Abstract: A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

Abstract: A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.

Abstract: A diode having an increased diode voltage drop is provided through the use of an extra collector-base contact which is left electrically floating. By leaving the extra collector-base contact electrically floating, a voltage divider effect results which provides an increased voltage drop across the diode without requiring other structural changes nor increased diode current.