Abstract: A circuit for varying the current to a load and, simultaneously, limiting the output of the load to a predetermined time interval. A timer chip having an RC network receives rectified current from an AC voltage source and responds thereto with a high output, which is used to bias an NPN transistor. The transistor permits the flow of rectified current to a logic triac, thereby triggering the logic triac and enabling current from the AC voltage source to flow to a variable resistor in series connection with a gating/AC timing capacitor, thereby triggering a diac. The diac responds to the controlled current flow from the variable resistor by operating the gate of a power control triac and permitting the desired current flow between the load and the AC voltage source through the power control triac.