Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and columns to be prepared are substituted with redundant memory columns.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair. Rows to be repaired are substituted with redundant memory rows and-columns-to be prepared are substituted with redundant memory columns.

Abstract: DRAM self-test circuitry performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. In another embodiment, the self-test circuitry also includes a mechanism for determining the performance of the addressed memory with respect to speed as well as accuracy. When either self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry.

Abstract: An on-chip testing device separately locates must-repairs or preferred-repairs in a row direction and column direction of a memory array. A row counter and a column counter are operated to index the memory array in row-major order, and then in column-major order (or vice versa). A running total of the number of failures is kept for each row and column, when the running total equals or exceeds a predetermined value, the row or column is determined to be a must-repair or a preferred repair.

Abstract: DRAM self-test circuitry, when triggered by an external signal, performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. When the self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry. The self-test circuitry further includes circuitry to detect data bit transitions between successive failing addresses latched in a the address queue.