Patents by Inventor Ray-Jane Ko

Ray-Jane Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interleaving architecture and method for a high density FIFO
    Patent number: 5663910
    Abstract: A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: September 2, 1997
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ray-Jane Ko, Fu Lam Au, Joseph P. Chiang
  • Interleaving architecture and method for a high density FIFO
    Patent number: 5546347
    Abstract: A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set.
    Type: Grant
    Filed: July 22, 1994
    Date of Patent: August 13, 1996
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ray-Jane Ko, Fu L. Au, Joseph P. Chiang