Abstract: A processor structure and method of operation are disclosed that comprise a user-configurable on-chip program memory system. The memory system comprises an on-chip memory 31 and a program memory controller 30 that reconfigures memory 31 in response to control values that may be modified by CPU core 20 under program control. In one mode, memory 31 may be mapped into internal address space. In other modes, memory 31 may be configured as an on-chip cache. In conjunction with the cache configuration, the program memory controller may comprise a tag RAM that is initialized upon a transition to cache mode. Program memory controller 30 handles memory mode transitions and data requests; CPU core 20 preferably requests stored instructions from controller 30 in a uniform fashion regardless of memory mode.