Abstract: The present invention relates to an arrangement for fastening a capacitor cup within which a capacitor is accommodated. The arrangement is for fastening a capacitor cup onto an opening of a mid-plate, wherein the capacitor cup comprises a cylindrical body having an opening end and an opposite end. The arrangement comprises: a collar provided on an outer surface of the cylindrical body, closely around the opening end; at least one first engagement feature formed at the outer surface of the cylindrical body and adjacent to the collar; and, at least one second engagement feature, corresponding to the first engagement feature, formed at an edge of the opening of the mid-plate; wherein, an engagement between the first and second engagement features fastens the capacitor cup onto the opening of the mid-plate.

Abstract: The present invention relates to an arrangement for fastening a capacitor cup within which a capacitor is accommodated. The arrangement is for fastening a capacitor cup onto an opening of a mid-plate, wherein the capacitor cup comprises a cylindrical body having an opening end and an opposite end. The arrangement comprises: a collar provided on an outer surface of the cylindrical body, closely around the opening end; at least one first engagement feature formed at the outer surface of the cylindrical body and adjacent to the collar; and, at least one second engagement feature, corresponding to the first engagement feature, formed at an edge of the opening of the mid-plate; wherein, an engagement between the first and second engagement features fastens the capacitor cup onto the opening of the mid-plate.

Abstract: A solar inverter is provided having a cooling module, a DC module, an inverter module and an AC module provided side-by-side within a chassis. The DC module includes an input accessible from a first side of the chassis and a disconnection switch on a second side of the chassis, with the input being configured to be connected to a DC solar power source. The AC module includes an output accessible from the first side of the chassis and a disconnection switch provided on the second side of the chassis. The cooling module is configured to pump a liquid coolant around the solar inverter in order to cool elements of the DC module, the inverter module and/or the AC module.

Abstract: A method for correcting for refraction effects of the earth's atmosphere in an emitter geolocation technique for locating an emitter of electromagnetic waves, by way of a plurality of receivers, includes detecting the times of arrival of electromagnetic waves at the receivers, computing the relative time differences of arrival between the various receivers and estimating therefrom the position of the emitter, and, for correcting, by way of an iterative procedure, the detected times of arrival for path length discrepancies caused by refraction in the earth's atmosphere. The receivers are each mounted on a respective airborne platform, and at least three pairs of the receivers are provided.

Abstract: A solar inverter is provided having a cooling module, a DC module, an inverter module and an AC module provided side-by-side within a chassis. The DC module includes an input accessible from a first side of the chassis and a disconnection switch on a second side of the chassis, with the input being configured to be connected to a DC solar power source. The AC module includes an output accessible from the first side of the chassis and a disconnection switch provided on the second side of the chassis. The cooling module is configured to pump a liquid coolant around the solar inverter in order to cool elements of the DC module, the inverter module and/or the AC module.

Abstract: A method and means for correcting for refraction effects of the earth's atmosphere in an emitter geolocation technique for locating an emitter of electromagnetic waves by means of a plurality of receivers, including detecting the times of arrival of electromagnetic waves at the receivers, computing the relative time differences of arrival between the various receivers and estimating therefrom the position of the emitter, and for correcting, by means of an iterative procedure, the detected times of arrival for path length discrepancies caused by refraction in the earth's atmosphere. The receivers are each mounted on a respective airborne platform, and at least three pairs of said receivers are provided.

Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Abstract: A programmable gate array includes test subsystems for testing various functional subsystems of the programmable gate array. A sequence of test methods, employing the test subsystems, test the functionality of the programmable gate array, taking into account the interdependencies of the various subsystems and accordingly enabling fault isolation therein.

Abstract: A memory system having split logical bit lines and interleaved pre-charge/access cycles is provided. A bit line access circuit supports multiple conductors per logical bit line and pre-charges the conductors before access cycles thereto. The access cycles for one logical bit line are performed simultaneous with the pre-charge cycles for another logical bit line by the access circuit. Virtual reading is provided for eliminated memory cells. The memory system can be used in a programmable gate array having memory cells distributed throughout for programming respective programmable resources.

Abstract: A given interconnect of a programmable gate array includes a programmable repeater circuit that enables selective isolation and testing of a select block of configured circuitry within the programmable gate array. The programmable repeater circuit includes an input node coupled to a first portion of the given interconnect and an output node coupled to a second portion of the given interconnect. A selective buffer circuit selectively outputs a buffered output signal to the output node that is related to a logic state at the input node. A signal storage circuit is also connected to the input node for selectively storing the logic state received from the input node. In a further embodiment, the signal storage circuit comprises an LSSD register. A primary latch of the LSSD register receives data selectively either from the input node, in accordance with a first clock signal, or alternatively from a secondary serial input node, in accordance with a second clock signal.

Abstract: A field programmable gate array has a plurality of programmable resources addressable per respective x and y dimensions of an x,y two dimensional array. A memory device provides a plurality of memory units that store configuration data for configuring associated programmable resources of the field programmable gate array. A controller addresses the memory device with an N-bit address for retrieving given configuration data. An address decoder and sequencer divides the N-bit address into first, second, and third portions and employs the first and third portions interchangeably, in accordance with the second portion, for addressing respective x and y dimensions of the plurality of programmable resources for selecting an associated programmable resource to be configured in accordance with the retrieved configuration data.