Patents by Inventor Ray Larson

Ray Larson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094310
    Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Partha Sarathi BASU, Dimitar Trifonov TRIFONOV, Tony Ray LARSON, Chao-Hsiuan TSAY
  • Patent number: 11899082
    Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: February 13, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Keith Ryan Green, Tony Ray Larson
  • Patent number: 11867773
    Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Partha Sarathi Basu, Dimitar Trifonov Trifonov, Tony Ray Larson, Chao-Hsiuan Tsay
  • Publication number: 20230400447
    Abstract: An waveguide on access tube (WOAT) system measures soil moisture by sensors placed at various depths of a medium, such as soil. The WOAT system includes a rigid tube into which an inflatable tube with various sensors bonded to it is inserted. Once in place, the rigid tube is removed and the inflatable tube and its sensor are inflated to the diameter of the hole or channel in which it is positioned. The ability to inflate the inflatable tube allows for the sensors on the inflatable tube to be force fit against the interior wall of the hole or channel for proper soil or ambient environment measurements.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 14, 2023
    Inventors: Scott Knudson Anderson, Andrew Relyea Horton, David James Anderson, Bradley Ray Larson
  • Patent number: 11557722
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: January 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Patent number: 11333719
    Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 17, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Dimitar Trifonov, Tony Ray Larson
  • Publication number: 20220075009
    Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 10, 2022
    Inventors: Keith Ryan Green, Tony Ray Larson
  • Publication number: 20220075007
    Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 10, 2022
    Inventors: Keith Ryan Green, Dimitar Trifonov, Tony Ray Larson
  • Patent number: 11061100
    Abstract: A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tony Ray Larson, Dimitar Trifonov, Chao-Hsiuan Tsay, Partha Sarathi Basu
  • Publication number: 20210159403
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Application
    Filed: January 6, 2021
    Publication date: May 27, 2021
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Patent number: 10892405
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Publication number: 20200400755
    Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.
    Type: Application
    Filed: June 1, 2020
    Publication date: December 24, 2020
    Inventors: Partha Sarathi BASU, Dimitar Trifonov TRIFONOV, Tony Ray LARSON, Chao-Hsiuan TSAY
  • Publication number: 20200393529
    Abstract: A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.
    Type: Application
    Filed: September 20, 2019
    Publication date: December 17, 2020
    Inventors: Tony Ray LARSON, Dimitar TRIFONOV, Chao-Hsiuan TSAY, Partha Sarathi BASU
  • Publication number: 20200357987
    Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ?1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ?1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Ming Li, Yiqi Tang, Jie Chen, Enis Tuncer, Usman Mahmood Chaudhry, Tony Ray Larson, Rajen Manicon Murugan, John Paul Tellkamp, Satyendra Singh Chauhan
  • Patent number: 10483920
    Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash
  • Publication number: 20180337639
    Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Inventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash
  • Patent number: 10003306
    Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 19, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Tony Ray Larson, Dimitar Trifonov Trifonov, Biraja Prasad Dash
  • Patent number: 9041246
    Abstract: A phase balancing system includes a load forecasting module, a phase unbalance identification module and a demand response module. The load forecasting module determines a load forecast for the distribution system for the period of interest and the phase unbalance identification module determines voltage unbalance on the distribution system for the period of interest. The demand response module estimates an available demand response on the distribution system for the period of interest and allocates an optimized demand response from the available demand response to minimize the voltage unbalance on the distribution system for the period of interest.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: May 26, 2015
    Assignee: General Electric Company
    Inventors: Jason Wayne Black, Kannan Natarajan Tinnium, Ronald Ray Larson, Xiaofeng Wang, Harjeet Johal
  • Patent number: 8744638
    Abstract: A method and system for controlling load in a utility distribution network are provided that initiates a shed event for a node in the distribution network by selecting premisess associated with the node that are participating in a demand response program to reduce the load at the node to desired levels. More specifically, the system and method provide for selecting only enough participating premisess associated with the node that are necessary to reduce the load to desired levels.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: June 3, 2014
    Assignee: General Electric Company
    Inventors: Rajesh Tyagi, Jason Wayne Black, Ronald Ray Larson, Augusto Ramon Sellhorn, Xiaofeng Wang
  • Publication number: 20140040431
    Abstract: A system includes an OPC UA server having a memory configured to provide an address space arranged into a plurality of reference nodes, in which each reference node is associated with data stored in a data source. The system further includes a processor configured to receive an OPC UA client request for the data associated with a particular reference node. The processor is also configured to request and receive from the data source the data associated with the particular reference node. The processor is further configured to reply to the OPC UA client request with the data received from the data source.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: General Electric Company
    Inventors: Dattaraj Jagdish Rao, Ronald Ray Larson, Katrina Marie Griffith, Stephen Daniel Tynor