Patents by Inventor Ray Li
Ray Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932775Abstract: A curable coating composition is provided having multi-functionalized acrylic copolymer and silicone imine resin curing agents. The acrylic copolymer of the curable coating composition has, in polymerized form, epoxy functionalized groups and cure compatibility groups and the silicone imine forms an amino-functional silicone in the presence of water. The coating compositions are useful in the field of superior weatherable and durable coatings and are useful to replace isocyanate-containing polyurethane based coatings. Also provided are coated articles produced from the curable composition.Type: GrantFiled: July 17, 2019Date of Patent: March 19, 2024Assignees: Dow Global Technologies LLC, Dow Siliicones CorporationInventors: Alan M. Piwowar, Ray E. Drumright, Erin B. Vogel, Gary M. Wieber, Patrick J. Fryfogle, Yanxiang Li, Susan M. Machelski, Paul J. Popa, Adam C. Tomasik, Gerald Lawrence Witucki
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Publication number: 20240069874Abstract: Methods and apparatuses are described for intelligent imputation of missing data in a machine learning (ML) dataset comprised of a plurality of features. Each feature includes a plurality of values, where at least a portion of the values for one or more features are missing. A server analyzes the ML dataset to generate characteristics of the missing values in the ML dataset. The server selects an imputation algorithm for filling in the missing values based upon the identified characteristics. The server determines a computing environment in which the imputation algorithm is executed based upon one or more of a size of the ML dataset or the selected algorithm. The server generates code that comprises instructions for executing the imputation algorithm on the ML dataset in the computing environment. The server integrates the code into an ML platform that executes the code to assign replacement values to the missing values.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Pu Li, Pranay Tiwari, Manish Worlikar, Alain Wilkinson, Ray Zhang
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Patent number: 11437485Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: December 22, 2020Date of Patent: September 6, 2022Assignee: HRL LABORATORIES, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Publication number: 20210404231Abstract: A hinge for a door or window has a door or window and a frame. The hinge has a first and a second hinge leaf pivotably connectable to each other. The first hinge leaf is connectable to the door/window or frame. The second hinge leaf is adjustably connectable to a base in turn connectable to the other of said door/window or frame. The second hinge leaf extends from the base in a first direction and the hinge comprises an adjustment mechanism with a cam and follower configured so that rotating the cam moves the second hinge leaf, relative to the base, in the first direction.Type: ApplicationFiled: June 24, 2021Publication date: December 30, 2021Applicant: ERA Home Security LimitedInventors: Robert Menear, Ray Li
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Publication number: 20210151578Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: ApplicationFiled: December 22, 2020Publication date: May 20, 2021Applicant: HRL Laboratories, LLCInventors: Yu CAO, Rongming CHU, Zijian "Ray" LI
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Patent number: 10903333Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: GrantFiled: July 28, 2017Date of Patent: January 26, 2021Assignee: HRL Laboratories, LLCInventors: Yu Cao, Rongming Chu, Zijian Ray Li
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Publication number: 20190165154Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Zijian "Ray" LI, Rongming CHU
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Publication number: 20180114837Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Publication number: 20180097081Abstract: A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.Type: ApplicationFiled: July 28, 2017Publication date: April 5, 2018Applicant: HRL Laboratories, LLCInventors: Yu CAO, Rongming CHU, Zijian Ray Li
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Patent number: 9773884Abstract: A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer.Type: GrantFiled: March 15, 2013Date of Patent: September 26, 2017Assignee: HRL Laboratories, LLCInventors: Rongming Chu, Zijan Ray Li, Karim Boutros
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Publication number: 20170047453Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.Type: ApplicationFiled: April 7, 2016Publication date: February 16, 2017Inventors: Rongming Chu, Yu Cao, Zijian "Ray" Li, Adam J. Williams
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Publication number: 20150349117Abstract: A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Inventors: Rongming CHU, Mary Y. Chen, Xu Chen, Zijian "Ray" Li, Karim S. Boutros
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Publication number: 20150311330Abstract: A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.Type: ApplicationFiled: April 25, 2014Publication date: October 29, 2015Applicant: HRL Laboratories, LLCInventors: Zijian "Ray" LI, Rongming CHU
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Publication number: 20140264361Abstract: A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Rongming Chu, Zijan Ray Li, Karim Boutros
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Publication number: 20090140382Abstract: A polysilicon silicide electric fuse device, comprising: a substrate; a semiconductor material layer disposed on said substrate, said semiconductor material layer includes lead-out areas of the same doping type at both ends, and an intermediate area of non-doping or having dopant concentration lower than those of said lead-out areas at both ends; and one or more burn-out areas is/are provided in said intermediate area; and a metal silicide layer is provided on said semiconductor material layer. Through the application of said polysilicon silicide electric fuse device, the burning out of said fuse device is thus controlled to within said intermediate area of no doping or light doping, hereby increasing the mean value and reducing distribution area of electrical resistance after burning out of a fuse, and alleviating the overheating of surrounding areas as caused by a current during the burning out of a fuse.Type: ApplicationFiled: November 25, 2008Publication date: June 4, 2009Inventors: Wen-Yu Gao, Min-Xia Wei, Ray Li, Ching-Dong Wang