Abstract: A vehicle control device includes a plurality of IC units, while maintaining the operational reliability. The vehicle control device includes an IC unit for performing image processing on outputs from cameras; an IC unit for performing recognition processing of an external environment of the vehicle; and an IC unit for performing judgment processing for cruise control of the vehicle. A control flow is provided so as to allow the IC unit to transmit a control signal to the IC units and. The control flow is provided separately from a data flow configured to transmit the output from the cameras, the image data, and the external environment data.

Abstract: A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.

Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

Abstract: The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Abstract: An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. The clock unit may have: a normal mode in which the output clock signal has a low amount of jitter and a normal clock rate to enable normal use of the electronic device, and a failure analysis mode in which the output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede the normal use. The clock unit may be protected against unauthorized re-activation of the normal mode. A method of protecting an electronic device against unauthorized use is also described.

Abstract: A method of controlling an operating mode of at least one processing module. The method comprises receiving an indication of the execution of at least one background task by the at least one processing module, aggregating an execution duration for the at least one background task on the at least one processing module, and configuring a lower power mode for the at least one processing module when the at least one background task is allocated to the at least one processing module for execution thereon if the aggregated execution duration for the at least one background task exceeds a threshold duration within an evaluation period.

Abstract: The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller.

Abstract: An electronic device comprising a clock unit and a processing unit connected to the clock unit is described. The clock unit may deliver an output clock signal for operating the processing unit in accordance with the output clock signal. The clock unit may have: a normal mode in which the output clock signal has a low amount of jitter and a normal clock rate to enable normal use of the electronic device, and a failure analysis mode in which the output clock signal has a high amount of jitter or a reduced clock rate, or a high amount of jitter combined with a reduced clock rate, to impede the normal use. The clock unit may be protected against unauthorized re-activation of the normal mode. A method of protecting an electronic device against unauthorized use is also described.

Abstract: A detector circuit for detecting the presence of a remote capacitive sensor having at least two terminals connected via a protection circuit that includes one or more capacitors, the detector circuit comprising: a current supply for changing the charge on the sensor and the protection circuit, a detector for measuring the voltage on one or more of the terminals; wherein the presence of the sensor is determined by changing the charge on the capacitive sensor and the one or more capacitors of the protection circuit in a predetermined manner such that the voltage measurement on the one or more terminals when the sensor is present is significantly different than when the sensor is absent.

Abstract: A microcontroller device comprising a receiver component configured to receive a one or more reset signals for the microcontroller device; an identification component configured to identify a source of the or each reset signals received by the receiver component; a time interval determining component configured to determine a length of a time interval in accordance with the identified source of the or each reset signals received by the receiver component; a voltage setting component configured to set a voltage of an output of the microcontroller device to a first value on receipt of a reset signal by the receiver component; and a control component configured to maintain the voltage of the output at the first value for the duration of the determined length of the time interval; and set the voltage of the output to a second value on substantial completion of the determined length of the time interval.

Abstract: A microprocessor may include a logic circuit for executing instructions of a data processing application. The microprocessor may have a timer system which includes a clock counter connected to a clock input for receiving a clock signal and counting a number of cycles of the clock signal. A clock comparator may be connected the clock counter and to a timer register in which a timer reference value can be stored. The clock comparator may compare a number of cycles of the clock signal with the timer reference value and generate a timer signal based on the comparison. The timer system may have a timer output for outputting timer signal. The timer system may include a control input for receiving a digital value representing a measured value of a sensed parameter of a device and a control register in which a control reference value can be stored. A control comparator may be connected the control input.

Abstract: A microcontroller device comprising a receiver component configured to receive a one or more reset signals for the microcontroller device; an identification component configured to identify a source of the or each reset signals received by the receiver component; a time interval determining component configured to determine a length of a time interval in accordance with the identified source of the or each reset signals received by the receiver component; a voltage setting component configured to set a voltage of an output of the microcontroller device to a first value on receipt of a reset signal by the receiver component; and a control component configured to maintain the voltage of the output at the first value for the duration of the determined length of the time interval; and set the voltage of the output to a second value on substantial completion of the determined length of the time interval.

Abstract: A microprocessor may include a logic circuit for executing instructions of a data processing application. The microprocessor may have a timer system which includes a clock counter connected to a clock input for receiving a clock signal and counting a number of cycles of the clock signal. A clock comparator may be connected the clock counter and to a timer register in which a timer reference value can be stored. The clock comparator may compare a number of cycles of the clock signal with the timer reference value and generate a timer signal based on the comparison. The timer system may have a timer output for outputting timer signal. The timer system may include a control input for receiving a digital value representing a measured value of a sensed parameter of a device and a control register in which a control reference value can be stored. A control comparator may be connected the control input.

Abstract: A detector circuit for detecting the presence of a remote capacitive sensor having at least two terminals connected via a protection circuit that includes one or more capacitors, the detector circuit comprising: a current supply for changing the charge on the sensor and the protection circuit, a detector for measuring the voltage on one or more of the terminals; wherein the presence of the sensor is determined by changing the charge on the capacitive sensor and the one or more capacitors of the protection circuit in a predetermined manner such that the voltage measurement on the one or more terminals when the sensor is present is significantly different than when the sensor is absent.

Abstract: An electronic device comprises a voltage regulator supplying a current to a load such as a micro-controller unit. The load controls the current provided to the load from the voltage regulator. Preferably, the load controls the level of current supplied to the load upon start-up, thereby avoiding power surges being drawn by the load.

Abstract: In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Abstract: A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.

Abstract: A hand-held tool for shaping and smoothing rough beads of highly viscous liquids or pastes, such as caulking compounds or putty, and composed of a long thin, essentially rigid core with a predetermined length to width ratio, and further having a flexible outer covering, tightly encasing the rigid core over all surfaces except for the extreme ends, with the outer covering made from either soft rubber, flexible foam, or transparent flexible plastic. The working end of the tool can be cut to a desired shape and eventually trimmed off for easy cleanup.

Abstract: Memory management in a data processing system (10) is achieved by using one or more timing bits (54) to specify a timing parameter of a memory (18, 19, 34). To implement this in some embodiments of the present invention, a memory array (32, 33, 42) is multiple-mapped in the physical memory map (70) of processor (12) and the address bits (54) associated with the multiple-mapping are used to directly control timing parameters of the memory arrays (32, 33, 42). This allows for flexible timing specifications to be derived quickly on an access by access basis without requiring any additional control storage overhead.