Patents by Inventor Ray McConnell
Ray McConnell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210112564Abstract: A method of mitigating start-of-packet interference in a millimetre waveband wireless mesh communications network which comprises a first plurality of network node devices each having a transceiver unit which includes a beamforming antenna device, and a second plurality of millimetre waveband wireless communications links each of which interconnects a respective pair of the transceiver units of the network node devices, the method comprising: allocating respective baseband centre frequencies to pairs of transceivers of the network node devices, which baseband centre frequencies are for use with respective communications links of the network, each such allocated baseband centre frequency being offset from at least one other allocated baseband centre frequency by a respective predetermined offset amount; and at a first transceiver of a selected pair of transceivers, encoding a data packet using an encoding signal having the baseband centre frequency allocated to the selected pair of transceivers, to generate anType: ApplicationFiled: February 20, 2019Publication date: April 15, 2021Applicant: BluWireless Technology LimitedInventor: Ray MCCONNELL
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Patent number: 10517054Abstract: A technique for providing a synchronised clock signal across a wireless mesh network is described. The technique includes choosing one of a plurality received radio frequency signals to provide a synchronisation signal to which a local clock signal can be synchronised.Type: GrantFiled: June 9, 2017Date of Patent: December 24, 2019Assignee: BLUWIRELESS TECHNOLOGY LIMITEDInventor: Ray McConnell
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Patent number: 10412694Abstract: A technique for providing a synchronized clock signal across a wireless mesh network is described. The technique includes choosing one of a plurality received radio frequency signals to provide a synchronization signal to which a local clock signal can be synchronized.Type: GrantFiled: June 9, 2017Date of Patent: September 10, 2019Assignee: BLUWIRELESS TECHNOLOGY LIMITEDInventor: Ray McConnell
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Patent number: 10198268Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes an instruction register (41) having a plurality of register entries, each of which is operable to store an instruction word therein, and a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16), and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.Type: GrantFiled: June 14, 2016Date of Patent: February 5, 2019Assignee: BLUWIRELESS TECHNOLOGY LIMITEDInventors: Ray McConnell, Ifor Powell
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Patent number: 9990204Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16) of the processing element, and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.Type: GrantFiled: June 14, 2016Date of Patent: June 5, 2018Assignee: BLUWIRELESS TECHNOLOGY LIMITEDInventors: Ray McConnell, Ifor Powell
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Publication number: 20170359792Abstract: A technique for providing a synchronised clock signal across a wireless mesh network is described. The technique includes choosing one of a plurality received radio frequency signals to provide a synchronisation signal to which a local clock signal can be synchronised.Type: ApplicationFiled: June 9, 2017Publication date: December 14, 2017Applicant: BLUWIRELESS TECHNOLOGY LIMITEDInventor: RAY MCCONNELL
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Publication number: 20170359789Abstract: A technique for providing a synchronised clock signal across a wireless mesh network is described. The technique includes choosing one of a plurality received radio frequency signals to provide a synchronisation signal to which a local clock signal can be synchronised.Type: ApplicationFiled: June 9, 2017Publication date: December 14, 2017Applicant: BLUWIRELESS TECHNOLOGY LIMITEDInventor: RAY MCCONNELL
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Patent number: 9836412Abstract: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.Type: GrantFiled: May 8, 2015Date of Patent: December 5, 2017Assignee: Rambus Inc.Inventor: Ray McConnell
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Publication number: 20160364241Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes an instruction register (41) having a plurality of register entries, each of which is operable to store an instruction word therein, and a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16), and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.Type: ApplicationFiled: June 14, 2016Publication date: December 15, 2016Applicant: BluWireless Technology LimitedInventors: Ray Mcconnell, Ifor Powell
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Publication number: 20160364238Abstract: A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16) of the processing element, and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.Type: ApplicationFiled: June 14, 2016Publication date: December 15, 2016Applicant: BluWireless Technology LimitedInventors: RAY MCCONNELL, IFOR POWELL
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Publication number: 20160283241Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.Type: ApplicationFiled: March 17, 2016Publication date: September 29, 2016Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
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Patent number: 9285793Abstract: A data processing unit combines a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration.Type: GrantFiled: October 20, 2011Date of Patent: March 15, 2016Assignee: BLUEWIRELESS TECHNOLOGY LIMITEDInventors: Ray McConnell, Paul Winser
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Publication number: 20150248353Abstract: A plurality of processing elements (PEs) include memory local to at least one of the processing elements in a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory. The network consists of nodes arranged linearly or in a grid to connect the PEs and their local memories to a common controller. The processor performs memory accesses on data stored in the memory in response to control signals sent by the controller to the memory. The local memories share the same memory map or space. The packet-switched network supports multiple concurrent transfers between PEs and memory. Memory accesses include block and/or broadcast read and write operations, in which data can be replicated within the nodes and, according to the operation, written into the shared memory or into the local PE memory.Type: ApplicationFiled: May 8, 2015Publication date: September 3, 2015Inventor: Ray MCCONNELL
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Publication number: 20150143073Abstract: A data processing system is described in which a plurality of data processing units 521 . . . 52N cooperate with one another in order to process incoming data packets or an incoming data stream. Tasks are managed using a task list which is accessible and updateable by each data processing unit.Type: ApplicationFiled: January 20, 2015Publication date: May 21, 2015Applicant: BLUWIRELESS TECHNOLOGY LIMITEDInventors: Paul Winser, RAY MCCONNELL
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Patent number: 9037836Abstract: An array of a plurality of processing elements (PEs) are in a data packet-switched network interconnecting the PEs and memory to enable any of the PEs to access the memory. The network connects the PEs and their local memories to a common controller. The common controller may include a shared load/store (SLS) unit and an array control unit. A shared read may be addressed to an external device via the common controller. The SLS unit can continue activity as if a normal shared read operation has taken place, except that the transactions that have been sent externally may take more cycles to complete than the local shared reads. Hence, a number of transaction-enabled flags may not have been deactivated even though there is no more bus activity. The SLS unit can use this state to indicate to the array control unit that a thread switch may now take place.Type: GrantFiled: January 11, 2011Date of Patent: May 19, 2015Assignee: Rambus Inc.Inventor: Ray McConnell
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Patent number: 8762691Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array. The apparatus includes an instruction controller operable to receive instructions from a plurality of instructions streams, and to transfer instructions from those instructions streams to the processing elements in the array, such that the data processing apparatus is operable to process a plurality of processing threads substantially in parallel with one another. A data transfer controller is provided which is operable to control transfer of data between the internal memory units associated with the processing elements, and memory external to the array.Type: GrantFiled: June 29, 2007Date of Patent: June 24, 2014Assignee: Rambus Inc.Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
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Publication number: 20140040909Abstract: A data processing system is described in which a plurality of data processing units 521 . . . 52N cooperate with one another in order to process incoming data packets or an incoming data stream. Tasks are managed using a task list which is accessible and updateable by each data processing unit.Type: ApplicationFiled: October 20, 2011Publication date: February 6, 2014Inventors: Paul Winser, Ray McConnell
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Publication number: 20130331954Abstract: A data processing unit combines a scalar processor and a heterogeneous processor which includes a vector processing array. The vector processing array includes a plurality of vector processors which are operable in a single instruction multiple data configuration.Type: ApplicationFiled: October 20, 2011Publication date: December 12, 2013Inventors: Ray McConnell, Paul Winser
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Patent number: 8174530Abstract: A data processing apparatus includes a plurality of processing elements arranged in a single instruction multiple data array for processing data relating to graphical primitives. Vertex data relating to graphical primitives is used as feedback data for the processing elements for additional processing.Type: GrantFiled: June 6, 2007Date of Patent: May 8, 2012Assignee: Rambus Inc.Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
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Patent number: 8171263Abstract: A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array.Type: GrantFiled: June 29, 2007Date of Patent: May 1, 2012Assignee: Rambus Inc.Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer