Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: A system and method for realizing a multi-camera system having two optical paths with a single processing path for the two optical paths. Such a multi-camera system typically includes a first image-capture device associated with a first optical train wherein the first image-capture device is typically pointed in a first direction (i.e., away from the user). The multi-camera system further includes a second image-capture device having a second optical train wherein the second image-capture device is typically pointed in a second direction (i.e., toward the user). The multi-camera system further includes a single processing block coupled to the first image-capture device and the second image-capture device. The processing block is typically operable to process image data captured at each image-capture device.

Abstract: An electronic circuit having built-in self testing capabilities for optimizing power consumption. Typically, the electronic circuit includes a component circuit that operates at some known or unknown optimal operating power level. Further, the electronic circuit includes a power supply coupled to the component circuit such that the power supply provides power to the component circuit. Further yet, the electronic circuit includes a test circuit coupled to the component circuit and coupled to the power supply. The test circuit is operable to monitor the power supplied to the component circuit and operable to control the power supply. In an iterative manner, the test circuit reduces the power supplied to the component circuit until the power supplied to the component circuit is operating at the optimal operating power level.

Abstract: A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sample is selected. Image signals from each pixel circuit in the selected row are routed to a different one of the plurality of column amplifiers when the APS image sensor is in the normal mode of operation. Image signals from a plurality of the pixel circuits in the selected row are routed to one of the plurality of column amplifiers when the APS image sensor is in the sub-sampling mode of operation.

Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: An active pixel sensor (APS) image sensor comprises an array of pixel circuits corresponding to rows and columns of pixels, a plurality of amplifiers that buffer signals output by the array of pixel circuits, and a plurality of sample and hold circuits that read the buffered signals. A routing mechanism is positioned between the array of pixel circuits and the plurality of amplifiers.

Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: Compact CMOS pixel sensors containing three or four total transistors and four or five control lines provide a high percentage of sensor area for the photodiode that measures light intensity. The CMOS pixel sensors thus have good light sensitivity. The CMOS pixel sensors also provide active reset operations yielding low noise when resetting node voltages. The low transistor count is achieved using the same transistors during both reset operations and readout operation. Reversing the current direction through a pixel sensor during readout allows the row selection transistor to act as a buffer for a transistor having a gate coupled to the photodiode node.

Abstract: A system and method for realizing a multi-camera system having two optical paths with a single processing path for the two optical paths. Such a multi-camera system typically includes a first image-capture device associated with a first optical train wherein the first image-capture device is typically pointed in a first direction (i.e., away from the user). The multi-camera system further includes a second image-capture device having a second optical train wherein the second image-capture device is typically pointed in a second direction (i.e., toward the user). The multi-camera system further includes a single processing block coupled to the first image-capture device and the second image-capture device. The processing block is typically operable to process image data captured at each image-capture device.

Abstract: An electronic circuit having built-in self testing capabilities for optimizing power consumption. Typically, the electronic circuit includes a component circuit that operates at some known or unknown optimal operating power level. Further, the electronic circuit includes a power supply coupled to the component circuit such that the power supply provides power to the component circuit. Further yet, the electronic circuit includes a test circuit coupled to the component circuit and coupled to the power supply. The test circuit is operable to monitor the power supplied to the component circuit and operable to control the power supply. In an iterative manner, the test circuit reduces the power supplied to the component circuit until the power supplied to the component circuit is operating at the optimal operating power level.

Abstract: A method for compensating for dark current in an image sensor array. In a representative embodiments, the method includes determining a nominal average dark current for the image sensor array, determining location of each pixel in the image sensor array, obtaining a nominal dark current associated with each pixel based on the nominal average dark current and on the location of the pixel, and subtracting the associated nominal dark current from the image signal for each pixel. At least two of the pixels have differing associated nominal dark currents. In other representative embodiments compensation values for dark currents and for differences in channel processing are determined during the same time period.

Abstract: An optical sensor array includes an array of pixel circuits. Each pixel circuit includes a photo detector and a voltage supply line. The voltage supply line from each pixel circuit is connected to a common node. A voltage supply input configured to be coupled to a voltage supply and to the common node supplies a voltage to each pixel circuit. A sensing circuit coupled to the common node senses signals from the common node and outputs at least one signal representative of an average intensity of light directed onto the array of pixel circuits.

Abstract: A CMOS image sensor implementing a low noise active reset operation uses control circuitry outside a pixel sensor array and transistors in a pixel sensor as parts of an amplifier that charges a photodiode node. In one configuration, a reference transistor in the control circuit controls a current mirrored to a column line, and each pixel sensor in the corresponding column contains a transistor that acts as half of a differential pair when the row containing the pixel sensor is selected. A 4-transistor pixel sensor can be implemented using only NMOS transistors with PMOS transistors in the control circuitry used to complete an amplifier circuit.

Abstract: Compact CMOS pixel sensors containing three or four total transistors and four or five control lines provide a high percentage of sensor area for the photodiode that measures light intensity. The CMOS pixel sensors thus have good light sensitivity. The CMOS pixel sensors also provide active reset operations yielding low noise when resetting node voltages. The low transistor count is achieved using the same transistors during both reset operations and readout operation. Reversing the current direction through a pixel sensor during readout allows the row selection transistor to act as a buffer for a transistor having a gate coupled to the photodiode node.

Abstract: An active pixel sensor arrangement that provides sub-sampling and reset of all pixel cells after sub-sampling. In one embodiment, logic is provided between sampled and non-sampled rows to propagate reset signals to the non-sampled rows when the sampled rows are reset. In another embodiment, reset of non-sampled rows is implemented with control logic.

Abstract: A method of sampling image signals generated by pixel circuits of an active pixel sensor (APS) image sensor. The APS image sensor supports a normal mode of operation and a sub-sampling mode of operation. The method includes providing a plurality of column amplifiers. A row of pixels circuits to sample is selected. Image signals from each pixel circuit in the selected row are routed to a different one of the plurality of column amplifiers when the APS image sensor is in the normal mode of operation. Image signals from a plurality of the pixel circuits in the selected row are routed to one of the plurality of column amplifiers when the APS image sensor is in the sub-sampling mode of operation.

Abstract: An active pixel sensor (APS) circuit which provides enhanced test and signal processing capabilities. APSs usually include pixel cells arranged in an array of rows and columns. Selectably enableable coupling conductors are provided between principal conductors in the array to permit a signal on one principal conductors to propagate to another principal conductors. The principal conductors include row, reset and column conductors. Signal propagation for testing purposes and for normal mode operation are disclosed.

Abstract: An optical sensor array includes an array of pixel circuits. Each pixel circuit includes a photo detector and a voltage supply line. The voltage supply line from each pixel circuit is connected to a common node. A voltage supply input configured to be coupled to a voltage supply and to the common node supplies a voltage to each pixel circuit. A sensing circuit coupled to the common node senses signals from the common node and outputs at least one signal representative of an average intensity of light directed onto the array of pixel circuits.

Abstract: An ESD protection circuit for a BICMOS IC device protects NMOS transistors (Q2) of internal CMOS gates (G2) from ESD events at a high potential power rail (VCC). Specifically the ESD protection circuit protects NMOS pulldown transistors coupled between a pullup bipolar emitter follower transistor (Q5) and the low potential power rail (GND). A PMOS current control transistor (QPESD) is coupled with primary current path between the high potential power rail (VCC) and the bipolar emitter follower transistor (Q5) for controlling current flow through the emitter follower transistor. An RC time constant circuit (R10,C1) is coupled between the high potential power rail (VCC) and low potential power rail (GND). The RC time constant circuit is constructed with a time constant for following power up events but not for following the faster ESD events at the high potential power rail.

Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay.