Abstract: A dynamic random access memory circuit achieves much higher data bandwidth by maximizing the number of memory cell rows that are held open and by indefinitely increasing the time that the rows are open. The boosted voltage of a pump circuit is directed to active rows according to the presence of a pump token. The pump token is present at one location in a circular shift register corresponding to a memory array. The concurrence of the token and a pump-enable signal causes that array to receive a boosted voltage independent of an array-select operation.

Abstract: A method of improving the boosted wordline compliance of a memory circuit. A wordline is grounded prior to boosting with a voltage greater than the circuit bias voltage (e.g. vdd) from a boost voltage generator. Grounding the wordline pulls the gate of a pass transistor to the bias voltage minus a threshold voltage and prepares the pass transistor to self-boost upon boosting the wordline. The transconductance of the pass transistor is improved, improving the charge transfer from the boost generator to the wordline, decreasing rise time. In another embodiment, an isolation transistor between the wordline select circuit and the pass transistor is boosted to provide additional pass transistor gate voltage.

Abstract: An output driver for mixed voltage systems includes an input line for receiving a signal to be output. The circuit also includes an overvoltage generator, coupled between the input line and an output stage. The overvoltage generator boosts a level of the signal to a second voltage before it reaches the output stage. A restore circuit is also provided which restores the second voltage with every transition of the input signal.

Abstract: A video memory device has a normal write mode and a block write mode, and includes a global write driver driving global input/output (I/O) lines, and a number of local write drivers, each driving local I/O lines coupled to a number of memory cells. Control circuitry is coupled to the global write driver and to the local write drivers, and is adapted to generate block write control signals and normal write control signals. The block write control signals cause the write data path to freeze during a block write cycle, thereby conserving power during block writes.

Abstract: A redundancy circuit for a multiport memory device with first and second memories includes a fuse programming circuit, shared between the first and second memories, for programming a first redundant address. A first address compare circuit compares a received address for the first memory with the first redundant address. The first address compare circuit generates a redundant address selection signal when the received address is the same as the first redundant address. A second address compare circuit compares a second received address for the second memory with the first redundant address. The second address compare circuit generates a redundant address selection signal when the received address is the same as the first redundant address.