Patents by Inventor Ray Simar
Ray Simar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11373720Abstract: The present disclosure describes analog memories for use in a computer, such as a computer using a combination of analog and digital components/elements used in a cohesive manner.Type: GrantFiled: February 22, 2019Date of Patent: June 28, 2022Assignee: OCTAVO SYSTEMS LLCInventors: Peter Linder, Laurence Ray Simar, Jr., Erik James Welsh, Gene Alan Frantz
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Patent number: 11347478Abstract: The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.Type: GrantFiled: February 22, 2019Date of Patent: May 31, 2022Assignee: OCTAVO SYSTEMS LLCInventors: Erik James Welsh, Laurence Ray Simar, Jr., Peter Linder, Gene Alan Frantz
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Patent number: 11171651Abstract: The present disclosure describes a mixed signal computer unit using a combination of analog and digital components/elements in a cohesive manner. Depending on the signals and data that need to be processed, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize the computational results and the performance of the computation. Operations may be controlled by one or more digital cores.Type: GrantFiled: February 22, 2019Date of Patent: November 9, 2021Assignee: OCTAVO SYSTEMS LLCInventors: Laurence Ray Simar, Jr., Erik James Welsh, Peter Linder, Gene Alan Frantz
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Publication number: 20210072958Abstract: The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.Type: ApplicationFiled: February 22, 2019Publication date: March 11, 2021Applicant: Octavo Systems LLCInventors: Erik James WELSH, Laurence Ray SIMAR, Jr., Peter LINDER, Gene Alan FRANTZ
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Publication number: 20200403618Abstract: The present disclosure describes a mixed signal computer unit using a combination of analog and digital components/elements in a cohesive manner. Depending on the signals and data that need to be processed, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize the computational results and the performance of the computation. Operations may be controlled by one or more digital cores.Type: ApplicationFiled: February 22, 2019Publication date: December 24, 2020Applicant: Octavo Systems LLCInventors: Laurence Ray SIMAR, Jr., Erik James WELSH, Peter LINDER, Gene Alan FRANTZ
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Publication number: 20200402601Abstract: The present disclosure describes analog memories for use in a computer, such as a computer using a combination of analog and digital components/elements used in a cohesive manner.Type: ApplicationFiled: February 22, 2019Publication date: December 24, 2020Applicant: Octavo Systems LLCInventors: Peter LINDER, Laurence Ray SIMAR, Jr., Erik James WELSH, Gene Alan FRANTZ
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Publication number: 20150283429Abstract: A golf club may include a control unit that detects a swing of the golf club and generates a signal based on at least one goal swing parameter during the swing of the golf club. The golf club may include a stimulation generation module, configured to generate a stimulation in response to the signal.Type: ApplicationFiled: April 8, 2015Publication date: October 8, 2015Applicant: William Marsh Rice UniversityInventors: Sid Mullick, Chelsea Rodrigues, Matthew Lopez, Yize Zhao, Roy Wu, Gary Woods, Laurence Ray Simar, JR.
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Patent number: 7886255Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria. The method selects a number of datapath clusters to avoid too many input/output ports in data registers.Type: GrantFiled: January 22, 2008Date of Patent: February 8, 2011Assignee: Texas Instruments IncorporatedInventors: Laurence Ray Simar, Jr., Reid E. Tatge
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Publication number: 20080177996Abstract: A method of integrated circuit programmed data processor design includes selecting a benchmark application, selecting an initial set of architecture parameters, reconfiguring a compiler for the selected architecture parameters, compiling the benchmark, reconfiguring a data processor simulator to the selected architecture parameters, running the complied benchmark on the reconfigured simulator, automatically synthesizing an integrated circuit physical layout and evaluating performance of the selected architecture parameters against predetermined criteria. The method varies the selected architecture parameters upon failure to meet criteria until evaluation of the selected architecture parameters meets the criteria.Type: ApplicationFiled: January 22, 2008Publication date: July 24, 2008Inventors: Laurence Ray Simar, Reid E. Tatge
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Patent number: 6895494Abstract: A subpipelined translation embodiment provides binary compatibility between current an future generations of DSPs. When retrieved from memory an entire fetch packet is assigned an operating mode (base instruction set or migrant instruction set) according to the current execution mode. The fetch packets from the instruction memory are parsed into execute packets and sorted by execution unit (dispatched) in a datapath shared by both execution modes (base and migrant). The two execution modes have separate control logic. Instructions from the dispatch datapath are decoded by either base architecture decode logic or the migrant architecture decode logic, depending on the execution mode bound to the parent fetch packet. Code processed by the migrant and base decode pipelines produces machine words that are selected by a multiplexer. The multiplexer is controlled by the operating mode bound to the fetch packet that produced the machine word.Type: GrantFiled: June 26, 2000Date of Patent: May 17, 2005Assignee: Texas Instruments IncorporatedInventors: Donald E. Steiss, Laurence Ray Simar, Jr.
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Patent number: 5983328Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: June 7, 1995Date of Patent: November 9, 1999Assignee: Texas Instruments IncorporatedInventors: James F. Potts, Jerald Gwyn Leach, L. Ray Simar, Jr.
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Patent number: 5964825Abstract: A general purpose microprocessor architecture enabling more efficient computations of a type in which Boolean operations and arithmetic operations conditioned on the results of the Boolean operations are interleaved. The microprocessor is provided with a plurality of general purpose registers ("GPRs" 102) and an arithmetic logic unit ("ALU" 104), capable of performing arithmetic operations and comparison operations. The ALU has a first input (108) and a second input (110), and an output (112), the first and second inputs receiving values stored in the GPRs. The output stores the results of the arithmetic logic unit operations in the GPRs. At least one of the GPRs is capable of receiving directly from the ALU a result of a Boolean operation. In one embodiment, at least one of the GPRs (PN) capable of receiving directly from the ALU a result of a Boolean operation is configured so as to cause the conditioning of an arithmetic operation of the ALU based on the value stored in the GPR.Type: GrantFiled: February 9, 1996Date of Patent: October 12, 1999Assignee: Texas Instruments IncorporatedInventors: Nat Seshan, Laurence Ray Simar, Jr.
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Patent number: 5958044Abstract: A method for controlling the execution of a microprocessor to cause it to execute a NOP instruction for a programmable number of sequential cycles. A NOP instruction is provided, that includes a predetermined OP code field identifying the NOP instruction as a programmably multiple NOP instruction. A predetermined count field is provided, representing the number of sequential cycles in which a NOP operation is to be performed by said microprocessor. The NOP instruction OP code field is read, as is the NOP instruction count field. In response thereto, a NOP operation is performed for the number of sequential cycles represented by said NOP instruction count field.Type: GrantFiled: January 20, 1998Date of Patent: September 28, 1999Assignee: Texas Instruments IncorporatedInventors: Richard A. Brown, Ray Simar, Natarajan Seshan
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Patent number: 5907864Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: January 29, 1998Date of Patent: May 25, 1999Assignee: Texas Instruments IncorporatedInventors: James F. Potts, Jerald Gwyn Leach, L. Ray Simar, Jr.
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Patent number: 5179689Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: July 10, 1990Date of Patent: January 12, 1993Assignee: Texas Instruments IncorporatedInventors: Jerald G. Leach, L. Ray Simar, Jr.
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Patent number: 5175841Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: January 2, 1990Date of Patent: December 29, 1992Assignee: Texas Instruments IncorporatedInventors: Surendar S. Magar, James F. Potts, Jerald G. Leach, L. Ray Simar, Jr.
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Patent number: 5109351Abstract: Layered arrays of nearest-neighbor connected computation cells plus an error computation layer provide a learning network.Type: GrantFiled: August 21, 1989Date of Patent: April 28, 1992Assignee: Texas Instruments IncorporatedInventor: L. Ray Simar, Jr.
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Patent number: 5099417Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: February 19, 1991Date of Patent: March 24, 1992Assignee: Texas Instruments IncorporatedInventors: Surendar S. Magar, James F. Potts, Jerald G. Leach, L. Ray Simar, Jr.
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Patent number: 4912636Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.Type: GrantFiled: March 13, 1987Date of Patent: March 27, 1990Inventors: Surendar S. Magar, James F. Potts, Jerald G. Leach, L. Ray Simar Jr.