Abstract: A Ternary/Content Addressable Memory (T/CAM) design is presented. The CAM includes a rule table implemented using a Random Access Module (RAM) storing n rule entries. An n-to-1 multiplexer module, responsive to a value C of a cycle counter, varying between 0 to n-1, provides a selected C'th rule entry to a comparator block which performs a comparison between the selected C'th rule entry and a matching key. The resulting comparison result together with the value C are used to decode the matched rule. In implementing a TCAM, a bitmask table implemented using a RAM module storing n bitmask entries is used. An n-to-1 multiplexer module, responsive to the value C provides a corresponding C'th bitmask to a masking module which modifies the comparison result to ignore a subgroup of results of bitwise comparisons between the C'th rule entry and the matching key.

Abstract: A Ternary/Content Addressable Memory (T/CAM) design is presented. The CAM includes a rule table implemented using a Random Access Module (RAM) storing n rule entries. An n-to-1 multiplexer module, responsive to a value C of a cycle counter, varying between 0 to n-1, provides a selected C'th rule entry to a comparator block which performs a comparison between the selected C'th rule entry and a matching key. The resulting comparison result together with the value C are used to decode the matched rule. In implementing a TCAM, a bitmask table implemented using a RAM module storing n bitmask entries is used. An n-to-1 multiplexer module, responsive to the value C provides a corresponding C'th bitmask to a masking module which modifies the comparison result to ignore a subgroup of results of bitwise comparisons between the C'th rule entry and the matching key.