Patents by Inventor Raymond A. Turi
Raymond A. Turi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications
Publication number: 20020132467Abstract: A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.Type: ApplicationFiled: January 14, 2002Publication date: September 19, 2002Inventors: Mark Fischer, Jigish D. Trivedi, Charles H. Dennison, Todd R. Abbott, Raymond A. Turi -
Patent number: 6444520Abstract: A method of fabricating conductive plugs of different conductive types in contact with different conductivity type semiconductor regions of a semiconductor substrate. The method of the present invention utilizes a simplified two-step masking process and results in a semiconductor device having low resistance conductive plugs of two different conductivity types. The conductive plugs may be formed from conductive materials such as doped polysilicon or refractory metal. If a refractory metal is used, a barrier layer of titanium nitride or titanium oxynitride is used to form the outer layer of the conductive plug.Type: GrantFiled: November 15, 2000Date of Patent: September 3, 2002Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Raymond A. Turi
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Patent number: 6429449Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: May 12, 2000Date of Patent: August 6, 2002Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Publication number: 20020102788Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: August 1, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20020102839Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: August 1, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Publication number: 20020098716Abstract: A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: ApplicationFiled: March 22, 2002Publication date: July 25, 2002Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6421282Abstract: A memory device having a plurality of programming circuits. The programming circuits connect to an input pad to receive a programming voltage. When one of the programming circuits is activated during a programming operation, the activated programming circuit passes the programming voltage to a programming node connected to it. Non-activated programming circuits only pass a portion of the programming voltage to other programming nodes connected to them.Type: GrantFiled: March 14, 2001Date of Patent: July 16, 2002Assignee: Micron Technology, Inc.Inventors: Huy Thanh Vo, Raymond A. Turi
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Patent number: 6391688Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: GrantFiled: October 23, 2000Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: Fernando N. M. Gonzalez, Raymond A. Turi
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Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications
Patent number: 6376358Abstract: A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.Type: GrantFiled: March 15, 2001Date of Patent: April 23, 2002Assignee: Micron Technology, Inc.Inventors: Mark Fischer, Jigish D. Trivedi, Charles H. Dennison, Todd R. Abbott, Raymond A. Turi -
Publication number: 20010055874Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: ApplicationFiled: July 16, 2001Publication date: December 27, 2001Inventors: Fernando Gonzalez, Raymond A. Turi
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Patent number: 6300684Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: GrantFiled: May 11, 1999Date of Patent: October 9, 2001Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi
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Patent number: 6223432Abstract: A method of fabricating conductive plugs of different conductive types in contact with different conductivity type semiconductor regions of a semiconductor substrate. The method of the present invention utilizes a simplified two-step masking process and results in a semiconductor device having low resistance conductive plugs of two different conductivity types. The conductive plugs may be formed from conductive materials such as doped polysilicon or refractory metal. If a refractory metal is used, a barrier layer of titanium nitride or titanium oxynitride is used to form the outer layer of the conductive plug.Type: GrantFiled: March 17, 1999Date of Patent: May 1, 2001Assignee: Micron Technology, Inc.Inventors: Charles H. Dennison, Raymond A. Turi
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Patent number: 6194746Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: September 9, 1998Date of Patent: February 27, 2001Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme
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Patent number: 6118135Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: July 6, 1998Date of Patent: September 12, 2000Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 6111264Abstract: A method for fabricating an ultra-small pore or contact for use in chalcogenide memory cells specifically and in semiconductor devices generally in which disposable spacers are utilized to fabricate ultra-small pores or contacts. The pores thus defined have minimum lateral dimensions ranging from approximately 500 to 4000 Angstroms. The pores thus defined may then be used to fabricate a chalcogenide memory cell or other semiconductor devices.Type: GrantFiled: November 13, 1997Date of Patent: August 29, 2000Assignee: Micron Technology, Inc.Inventors: Graham R. Wolstenholme, Steven T. Harshfield, Raymond A. Turi, Fernando Gonzalez, Guy T. Blalock, Donwon Park
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Patent number: 6104038Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: GrantFiled: May 11, 1999Date of Patent: August 15, 2000Assignee: Micron Technology, Inc.Inventors: Fernando N. M. Gonzalez, Raymond A. Turi
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Patent number: 6002140Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: GrantFiled: April 30, 1997Date of Patent: December 14, 1999Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi
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Patent number: 5985698Abstract: A vertically oriented diode for use in delivering current to a multi-state memory element in a memory cell. A vertical diode may be disposed in a diode container extending downwardly from a top of a silicon or oxide layer, and may be formed of a combination of silicon and/or metal layers disposed proximate to inner surfaces of a diode container. A multi-state memory element may be formed of a multi-state material, such as a chalcogenide, above a diode to complete a memory cell.Type: GrantFiled: April 30, 1997Date of Patent: November 16, 1999Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi, Graham R. Wolstenholme, Charles L. Ingalls
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Patent number: 5879955Abstract: A method for fabricating an array of ultra-small pores for use in chalcogenide memory cells. A layer of a first material is applied onto a substrate. A portion of the layer of the first material is then removed to define an upper surface with vertical surfaces extending therefrom to a lower surface in the first layer of the first material. A fixed layer of a second material is then applied onto the vertical surfaces of the first layer of the first material. The fixed layer of the second material has a first thickness. A second layer of the first material is then applied onto the fixed layer of the second material. The fixed layer of the second material is then removed to define an array of pores in the first material layers. The pores thus defined have minimum lateral dimensions ranging from approximately 50 to 500 Angstroms and cross sectional areas greater than or equal to the first thickness of the second layer squared.Type: GrantFiled: June 7, 1995Date of Patent: March 9, 1999Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Raymond A. Turi
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Patent number: 5854102Abstract: A vertical diode is provided having a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.Type: GrantFiled: September 5, 1997Date of Patent: December 29, 1998Assignee: Micron Technology, Inc.Inventors: Fernando Gonzalez, Tyler A. Lowrey, Trung Tri Doan, Raymond A. Turi, Graham R. Wolstenholme