Patents by Inventor Raymond Alan Jackson

Raymond Alan Jackson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6259155
    Abstract: A ceramic column grid array package suitable for mounting application specific integrated circuits or microprocessor chips onto a printed circuit board employing polymer reinforced columns on the substrate module is described. The polymer enhancement is formed by coating a thin conformal film of a polymer, such as, a polyimide onto the substrate module after the formation of the ceramic column grids to mechanically enhance the column to substrate attachment of the column to the substrate prior to mounting on a printed circuit card. Upon curing of the polymer film at a temperature below the melting point of the solder bond attaching the column grid to the substrate, the columns will be mechanically reinforced in their attachment to the substrate. Upon removal of the substrate module from a printed circuit card during rework, the columns of the grid array will remain with the substrate module, leaving no columns on the printed circuit card.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Mario John Interrante, Raymond Alan Jackson, Sudipta Kumar Ray, Paul A. Zucco, Scott R. Dwyer
  • Patent number: 6226863
    Abstract: A device and method for enabling the reworkability of an integrated circuit comprising a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Mukta Shaji Farooq, Raymond Alan Jackson, Sudipta Kumar Ray
  • Patent number: 6070782
    Abstract: An electronic component having a socketable bump grid array comprising shaped-solder coated metallic spheres is provided by a method which comprises positioning solder coated metal spheres in an aligning device having a plurality of openings corresponding to the array, the openings being tapered preferably in the form of a truncated cone with the base of the cone being at the upper surface of the aligning device and having a diameter larger than the diameter of the solder coated metal sphere. The opening is configured so that a sphere positioned in the opening extends partially above the upper surface of the aligning device. The pads of the substrate are then contacted with the positioned spheres and, when the solder is reflowed, the solder forms a bond between the conductive layer on the substrate in contact with the solder-coated metal sphere and takes the shape of the aligning device and which maintains a solder coating on the whole surface of the metal sphere.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: June 6, 2000
    Assignee: International Business Machines Corporation
    Inventors: Peter Jeffrey Brofman, Balaram Ghosal, Raymond Alan Jackson, Kathleen Ann Lidestri, Karl J. Puttlitz, Sr., William Edward Sablinski
  • Patent number: 6015955
    Abstract: A device and method for enabling the reworkability of an integrated circuit. The device includes a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: January 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mukta Shaji Farooq, Raymond Alan Jackson, Sudipta Kumar Ray
  • Patent number: 5868304
    Abstract: An electronic component having a socketable bump grid array comprising shaped-solder coated metallic spheres is provided by a method which comprises positioning solder coated metal spheres in an aligning device having a plurality of opening corresponding to the array, the openings being tapered preferably in the form of a truncated cone with the base of the cone being at the upper surface of the aligning device and having a diameter larger than the diameter of the solder coated metal sphere. The opening is configured so that a sphere positioned in the opening extends partially above the upper surface of the aligning device. The pads of the substrate are then contacted with the positioned spheres and, when the solder is reflowed, the solder forms a bond between the conductive layer on the substrate in contact with the solder-coated metal sphere and takes the shape of the aligning device and which maintains a solder coating on the whole surface of the metal sphere.
    Type: Grant
    Filed: July 2, 1996
    Date of Patent: February 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: Peter Jeffrey Brofman, Balaram Ghosal, Raymond Alan Jackson, Kathleen Ann Lidestri, Karl J. Puttlitz, Sr., William Edward Sablinski
  • Patent number: 5779133
    Abstract: Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.
    Type: Grant
    Filed: May 1, 1996
    Date of Patent: July 14, 1998
    Assignee: International Business Machines Corporation
    Inventors: Raymond Alan Jackson, Kathleen Ann Lidestri, David Clyde Linnell, Raj Navinchandra Master