Abstract: Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

Abstract: Methods and systems of synchronizing events using a plurality of sequencing controllers are provided. For each sequencing controller, a serial communication bus (SCB) is monitored for a first reference level. Upon identifying that the SCB is at the first reference level for a predetermined period, a bit sequence indicative of an event position is broadcast to be arbitrated on the SCB. The SCB is monitored for the arbitrated bit sequence. Upon determining that the arbitrated bit sequence corresponds to the bit sequence of the event position, an event corresponding to the event position is enabled.

Abstract: A power control system includes an event data bus configured to carry event information. Several power supply managers are coupled to the same event bus. Each power supply manager has one or more point of load (POL) regulators assigned to it. Each power supply manager communicates event information with other POL power supply managers over the event data bus.

Abstract: A power control system includes an event data bus configured to carry event information. Several power supply managers are coupled to the same event bus. Each power supply manager has one or more point of load (POL) regulators assigned to it. Each power supply manager communicates event information with other POL power supply managers over the event data bus.

Abstract: A data queue control submodule supporting a host processor and at least one peripheral device. The submodule includes a memory unit with a first memory portion for storing queue commands associated with each peripheral device and a second memory portion for storing peripheral device data. A queue control unit is also included in the submodule for controlling the flow of data between the peripheral devices and the host processor in accordance with the queue control commands. A port interface connects the queue control unit and the peripheral devices in response to a trigger event. The submodule further includes an event controller in communication with the host processor and the port interface for generating event triggers in response to data demands of either the host processor or the other peripheral devices. The present invention is advantageous in that it simplifies the design of each port interface and provides improved flexibility in the queue structure of the overall control system.