Abstract: In an electronic device, a method includes analyzing help information associated with a software application to identify a sequence of manipulations of viewable elements associated with an instance of an operation by the software application. The method further includes generating a voice command set based on the sequence of manipulations of viewable elements and storing the voice command set. The method further includes receiving voice input from a user, determining the voice input represents a voice command of the voice command set, and performing an emulated manipulation sequence of viewable elements based on the voice command to actuate an instance of the operation by the software application, the emulated manipulation sequence based on the sequence of manipulations of viewable elements.

Abstract: A method and apparatus for voice operation of mobile applications having unnamed view elements includes an electronic computing device configured to determine that a view element for a mobile application is unnamed in a view hierarchy layout file for the mobile application and to enter a name for the view element in a data record. The method performed by the electronic computing device further includes receiving a voice command for an operation that invokes the view element. Additionally included in the method is determining, using the name for the view element, display coordinates for the view element and actuating the view element using the display coordinates.

Abstract: In an electronic device, a method includes analyzing help information associated with a software application to identify a sequence of manipulations of viewable elements associated with an instance of an operation by the software application. The method further includes generating a voice command set based on the sequence of manipulations of viewable elements and storing the voice command set. The method further includes receiving voice input from a user, determining the voice input represents a voice command of the voice command set, and performing an emulated manipulation sequence of viewable elements based on the voice command to actuate an instance of the operation by the software application, the emulated manipulation sequence based on the sequence of manipulations of viewable elements.

Abstract: In an electronic device, a method comprises monitoring a user's tactile manipulation of viewable elements of the electronic device to determine a viewable element manipulation sequence that actuates a first instance of an operation by at least one software application of the electronic device. The method further includes determining a set of attributes associated with the viewable elements and determining a command syntax for the operation based on the first viewable element manipulation sequence and the set of attributes. The method further includes generating a voice command set based on the command syntax and storing the voice command set. The method further includes receiving voice input from a user and determining the voice input represents a voice command of the voice command set. The method further includes performing an emulation of the viewable element manipulation sequence based on the voice command to actuate a second instance of the operation.

Abstract: A method and apparatus for scheduling project meetings includes a meeting organizer module of an electronic computing device receiving, from a project manager module, a first criticality for a first task and a second criticality for a second task of a plurality of tasks for a project. The method also includes the meeting organizer module scheduling a project meeting for the project based on the first criticality and the second criticality, wherein scheduling the project meeting includes determining an ordered agenda in which presentations for tasks for the project are presented for the project meeting.

Abstract: In a method of executing a program on an interpreted bytecode language, a plurality of interpreted bytecode modules (each having an associated name) is loaded. A pointer is directed from each method entry to a different interpreted bytecode module. A native code module library is loaded and includes a native code module (also having an associated name) that implements a function corresponding to an interpreted bytecode module. When the name of an interpreted bytecode module corresponds to the name of a native code module, the pointer directed to the interpreted bytecode module is redirected to the corresponding native code module. Each interpreted bytecode module and native code module pointed to by the each method entry in the method table is executed according to an application-controlled order of execution.

Abstract: A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to ‘invalid’ in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to ‘valid’. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.

Abstract: A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to ‘invalid’ in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to ‘valid’. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.

Abstract: A method for generating a sequence of memory addresses for a multi-dimensional data structure and an address generation unit are disclosed. The address generation unit includes an ADDRESS register, a STRIDE register, and a plurality skip generators, each having SKIP, SPAN and COUNT registers. An address value is initialized to a first address and each COUNT register is initialized. For each address of the sequence an address value is output and a stride value is added to the address value. For each dimension of the data structure the COUNT register associated with the dimension is updated as each address is generated. For all dimensions, when the COUNT register value becomes zero, the skip value associated with the dimension is added to the address value and its COUNT register is reset to a specified value.

Abstract: A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate result tagged with a data validity tag. The data validity tags indicate the validity of the data. Before a loop is executed, the data validity tags are set to indicate that the associated data values are invalid. During execution of the loop body a functional unit checks the validity of input data. If all of the input data values are valid the functional operation is performed, the corresponding data validity tag set to indicate that the result is valid. If any of the input data values is invalid, the data validity tag of the result is set to indicate that the result is invalid. To eliminate the epilog, an iteration counter is associated with each sink unit of the vector processor.

Abstract: In a method of executing a program on an interpreted bytecode language, a plurality of interpreted bytecode modules (each having an associated name) is loaded. A pointer is directed from each method entry to a different interpreted bytecode module. A native code module library is loaded and includes a native code module (also having an associated name) that implements a function corresponding to an interpreted bytecode module. When the name of an interpreted bytecode module corresponds to the name of a native code module, the pointer directed to the interpreted bytecode module is redirected to the corresponding native code module. Each interpreted bytecode module and native code module pointed to by the each method entry in the method table is executed according to an application-controlled order of execution.

Abstract: System and method for receiving a call in a wireless device. A notification message is received over a first radio access technology (RAT) that another wireless device wants to engage in the call. At least one other RAT is identified that can be utilized to connect the call. The at least one other RAT is selected to connect the call. A connection is initiated through utilization of the at least one other RAT.

Abstract: Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be used to indicate a maximum number of vector elements that may be transferred to or from a single register within a register file. Also, the instructions may use a variety of different addressing modes. The memory element size may be specified independently from the register element size such that source and destination sizes may differ within an instruction. With some instructions, a vector stream may be initiated and conditionally enqueued or dequeued. Truncation or rounding fields may be provided such that source data elements may be truncated or rounded when transferred. Also, source data elements may be sign- or unsigned-extended when transferred.

Abstract: A cache for storing data elements is disclosed. The cache includes a cache memory having one or more lines and one or more cache line counters, each associated with a line of the cache memory. In operation, a cache line counter of the one or more of cache line counters is incremented when a request is received to prefetch a data element into the cache memory and is decremented when the data element is consumed. Optionally, one or more reference queues may be used to store the locations of data elements in the cache memory. In one embodiment, data cannot be evicted from cache lines unless the associated cache line counters indicate that the prefetched data has been consumed.

Abstract: A bus filter includes a first bus interface connected to a system bus for receiving a virtual memory address and a second interface connected to the system bus for transmitting a physical memory address. In operation, an address translation unit, such as a translation lookaside buffer, determines the physical memory address from the virtual memory address. The bus filter may be used to couple a processing device, such as an accelerator, to a system having a core processor and an external memory unit coupled by a bus.

Abstract: A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch (104) and a micro-sequencer (118). The re-configurable interconnection switch (104) includes one or more links, each link operable to couple an output of a function unit (102) to an input of a function unit (102) as directed by the micro-sequencer (118). The vector processor may also include one or more input-stream units (122) for retrieving data from memory. Each input-stream unit is directed by a host processor and has a defined interface (116) to the host processor. The vector processor also includes one or more output-stream units (124) for writing data to memory or to the host processor. The defined interface of the input-stream and output-stream units forms a first part of the programming model.

Abstract: A method for scheduling a computation for execution on a computer with a number of interconnected functional units. The computation is representable by a data-flow graph with a number of nodes connected by edge. A loop-period of the computation is calculated and the nodes are scheduled for throughput by assigning an execution cycle and a functional unit to each node of the data-flow graph. The scheduling of flexible nodes is adjusted to minimize the number of interconnections required in each execution cycle. The edges of the data-flow graph are allocated to one or more of the interconnections between functional units. The scheduling method may be used, for example, to optimize the interconnection fabric design for an ASIC or as part of a compiler for a re-configurable streaming vector processor.

Abstract: A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as registers, and an arithmetic unit for calculating a memory address of a vector element dependent upon values stored in the storage elements and the address of a previous vector element. The storage elements hold STRIDE, SKIP and SPAN values and optionally a TYPE value, relating to the spacing between elements in the same partition, the spacing between elements in the consecutive partitions, the number of elements in a partition and the size of a vector element, respectively.

Abstract: A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each input of the data-flow graph, a computational instruction is generated for each node of the data-flow graph, and a sink instruction is generated for each output of the data-flow graph. The computational instruction for a node includes a descriptor of an operation performed at the node and a descriptor of each instruction that produces an input to the node. The formatted description is a sequential instruction list comprising source instructions, computational instructions and sink instructions. Each instruction has an instruction identifier and the descriptor of each instruction that produces an input to the node is the instruction identifier. The computer is directed by a program of instructions to implement a computation representable by a data-flow graph.

Abstract: An interconnection device (300) with a number of links (306, 308, 310, 312 and 314), each link having a number of link input ports (302), link output ports (304) and storage registers (316). An input selection switch (402) is coupled to a selected link input port to receive an input data token. The storage registers (316) may be used to store input data tokens. A storage access switch (404) is coupled to the input selection switch (402) and to the storage registers (316) and may be used to select the current input data token or a token from the storage registers as an output data token. An output selection switch (406) receives the output data token and provides it to a selected link output port. The interconnection device may, for example, be used to connect the inputs and outputs of the processing elements of a vector processor or digital signal processor.