Abstract: A stable high-frequency clock pulse apparatus and method including frequency source, overtone crystal unit coupled with a negative resistance oscillator, a bandpass overtone filter and a drive level control is provided. The apparatus can include a frequency multiplier. The frequency source can be a micromechanical resonator.

Abstract: A drive circuitry that drives a vertical cavity surface emitting laser is provided. The drive circuitry includes a modulator, a negative peak timer and a limiter. The negative peak timer causes the modulator to rapidly decrease the magnitude of the output signal of the modulator to dissipate charge stored on the laser. Thus, the vertical cavity surface emitting laser quickly turns off.

Abstract: An electrocardiographic amplifier having an integrator in the feedback loop between the amplifier's input and output whose time constant is varied by the duty cycle of a series switch to vary the low frequency 3 dB roll-off point as a function of the detected low frequency noise in the amplifier output signal. A capacitor is switched in parallel with the inverting feedback resistor to lower the high frequency 3 dB roll-off point in response to detected high frequency noise.

Abstract: A compensation device for the base of emitter follower configured bipolar transistors becoming operable at elevated temperatures including a bipolar transistor of a geometry of not more than half the geometry of the bipolar emitter follower having its collector connected to the base of the emitter follower and its base and emitter connected together and to the emitter of the emitter follower.

Abstract: A high temperature current mirror amplifier having biasing means in the transdiode connection of the input transistor for producing a voltage to maintain the base-collector junction reversed-biased and a current means for maintaining a current through the biasing means at high temperatures so that the base-collector junction of the input transistor remained reversed-biased. For accuracy, a second current mirror is provided with a biasing means and current means on the input leg.

Abstract: An amplifier circuit including a FET inverter with its N channel device being part of the controlled leg of a first current mirror, and its P channel device being part of the controlled leg of a second current mirror. The operating point of the inverter is the reference signal applied on the input to the current mirrors.

Abstract: A new encoder for an analog to digital converter of the successive approximation type incorporates instrumentation amplifier and signal sample and hold functions within the encoder proper, thereby substantially simplifying the converter circuitry. An input analog current signal is applied to a sample and hold capacitor within the encoder through the encoder comparator at a time when the weighted reference signal to the comparator is set to zero. The capacitor stored analog voltage is subsequently applied to the encoder summing node and the encoding sequence ensues. The encoder may be provided with offset and gain correction circuitry, conventionally found exterior to the encoder. In one embodiment of the invention, offset correction is effected using the signal sample and hold capacitor.

Abstract: A current source having two current paths connected as current mirrors with an amorphous material device in one of the current paths which is electrically alterable from a high impedance state to lower high impedance states without switching to a low impedance state. A diode interconnects the amorphous material element to the current path to prevent damage to the current path during electrical alteration of the amorphous material device. The current source is included in a differential amplifier and operational amplifier to provide fine incremental trim or offset adjustment.

Abstract: A CMOS voltage multiplier circuit comprised of one or more multiplier cells each of said cells including two P-channel devices functioning as switching elements to connect a cell contained capacitance in parallel across a voltage supply during one half of a cycle and a single N-channel device for connecting the capacitance in series with the supply during the other half of the cycle. An output stage is provided which includes a transfer device and a modified multiplier cell for driving the transfer device.

Abstract: A CMOS oscillator including a first pair of series connected CMOS devices and second pair of series connected CMOS devices, a resistance connected to the source of one of said MOS devices of the first pair having a width to length ratio greater than the width to length ratio of the corresponding device of the second pair, and a series resonant frequency determining network. The resistance and the larger W/L MOS device determine the steady state operating current independent of other circuit elements. The gates of the one MOS device and corresponding MOS devices are connected to the drain of the corresponding device and the other MOS devices are connected as current mirrors.